FS#58195 - [i7z] Sleep state reporting is broken for Sandy Bridge

Attached to Project: Community Packages
Opened by Adam Fontenot (amfontenot) - Wednesday, 11 April 2018, 00:22 GMT
Last edited by Sven-Hendrik Haase (Svenstaro) - Friday, 13 April 2018, 10:18 GMT
Task Type Bug Report
Category Upstream Bugs
Status Closed
Assigned To Sven-Hendrik Haase (Svenstaro)
Architecture All
Severity Low
Priority Normal
Reported Version
Due in Version Undecided
Due Date Undecided
Percent Complete 100%
Votes 0
Private No

Details

Description:
There's a dead simple bug in the code that prevents i7z from accurately reporting when a core is in the C7 sleep state. It reports it as in C0 instead. This is because the CPU detection code is missing one of the cases. See here: https://github.com/ajaiantilal/i7z/blob/master/helper_functions.c#L395

The missing case is
if (proc_info.extended_model == 0x2 && proc_info.model == 0xA) *sandy_bridge = true;

You can see Intel's documentation on this here: http://software.intel.com/en-us/articles/intel-processor-identification-with-cpuid-model-and-family-numbers/

Since the development on i7z has been stopped for about 5 years, it would be nice to slip a little patch into the Arch package to fix this. Alternatively, I've spent most of today improving the codebase and fixing a number of bugs. It's not very well-written code, and had a number of hacks to work around some bad asm that would otherwise result in segfaults. So you could point the PKGBUILD at my cleaner fork which is here: https://github.com/afontenot/i7z
This task depends upon

Closed by  Sven-Hendrik Haase (Svenstaro)
Friday, 13 April 2018, 10:18 GMT
Reason for closing:  Fixed
Comment by Sven-Hendrik Haase (Svenstaro) - Wednesday, 11 April 2018, 16:54 GMT
Cool stuff. Switching to your fork. Can you make a release?
Comment by Adam Fontenot (amfontenot) - Thursday, 12 April 2018, 23:56 GMT
Done. https://github.com/afontenot/i7z/releases/tag/v0.28

I expect future improvements to be a bit slower, but there are still some fixes likely needed for proper detection of post-Haswell processors.

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