FS#48120 - [libx86] trap invalid opcode in libx86.so
Attached to Project:
Community Packages
Opened by Jody (jfrankowski) - Wednesday, 10 February 2016, 17:09 GMT
Last edited by Kyle Keen (keenerd) - Tuesday, 06 December 2016, 06:27 GMT
Opened by Jody (jfrankowski) - Wednesday, 10 February 2016, 17:09 GMT
Last edited by Kyle Keen (keenerd) - Tuesday, 06 December 2016, 06:27 GMT
|
Details
Description:
get-edid crashes in libx86.so with the following error: This is read-edid version 3.0.2. Prepare for some fun. Attempting to use i2c interface Looks like no busses have an EDID. Sorry! Attempting to use the classical VBE interface [1] 25943 illegal hardware instruction (core dumped) get-edid And the following kernel error: [67068.734752] traps: get-edid[25943] trap invalid opcode ip:7f691ff019cf sp:7ffd1203ccd0 error:0 in libx86.so.1[7f691fefa000+1f000] Additional info: libx86 version 1.1-5 read-edid version 3.0.2-1 
coredump.lz4
(35.7 KiB)
|
This task depends upon
Closed by Kyle Keen (keenerd)
Tuesday, 06 December 2016, 06:27 GMT
Reason for closing: Fixed
Additional comments about closing: libx86 1.1-6
Tuesday, 06 December 2016, 06:27 GMT
Reason for closing: Fixed
Additional comments about closing: libx86 1.1-6
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 8
On-line CPU(s) list: 0-7
Thread(s) per core: 2
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 94
Model name: Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
Stepping: 3
CPU MHz: 800.000
CPU max MHz: 4200.0000
CPU min MHz: 800.0000
BogoMIPS: 8019.90
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 256K
L3 cache: 8192K
NUMA node0 CPU(s): 0-7
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch ida arat epb pln pts dtherm hwp hwp_notify hwp_act_window hwp_epp intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm mpx rdseed adx smap clflushopt xsaveopt xsavec xgetbv1
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 4
On-line CPU(s) list: 0-3
Thread(s) per core: 2
Core(s) per socket: 2
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 60
Model name: Intel(R) Core(TM) i3-4330 CPU @ 3.50GHz
Stepping: 3
CPU MHz: 2080.859
CPU max MHz: 3500.0000
CPU min MHz: 800.0000
BogoMIPS: 7000.41
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 256K
L3 cache: 4096K
NUMA node0 CPU(s): 0-3
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid xsaveopt dtherm arat pln pts
FS#51723:> In libx86's backend for x86_64 (thunk.c) there is an intentional zero deref:
> *((char *)0) = 0x4f; /* Make sure that we end up jumping back to a halt instruction */
> Assuming this can't be right GCC inserts an undefined instruction after this.
> Compiler flags "-fno-delete-null-pointer-checks" disables this behavior.