//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Thu Oct 31 02:24:44 2013 (1383182684)
// Driver 331.20
//

.version 3.0
.target sm_11, texmode_independent
.address_size 32

.const .align 4 .b8 __GPU_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};

.entry Convolve(
	.param .u32 .ptr .global .align 16 Convolve_param_0,
	.param .u32 .ptr .global .align 16 Convolve_param_1,
	.param .u32 Convolve_param_2,
	.param .u32 Convolve_param_3,
	.param .u32 .ptr .const .align 4 Convolve_param_4,
	.param .u32 Convolve_param_5,
	.param .u32 Convolve_param_6,
	.param .u32 Convolve_param_7,
	.param .u32 Convolve_param_8,
	.param .u32 .ptr .shared .align 16 Convolve_param_9,
	.param .u32 .ptr .shared .align 4 Convolve_param_10
)
{
	.reg .f32 	%f<179>;
	.reg .pred 	%p<20>;
	.reg .s32 	%r<184>;


	ld.param.u32 	%r6, [Convolve_param_5];
	ld.param.u32 	%r7, [Convolve_param_6];
	// inline asm
	mov.u32 	%r66, %envreg0;
	// inline asm
	// inline asm
	mov.u32 	%r67, %ctaid.x;
	// inline asm
	add.s32 	%r79, %r67, %r66;
	// inline asm
	mov.u32 	%r68, %envreg1;
	// inline asm
	// inline asm
	mov.u32 	%r69, %ctaid.y;
	// inline asm
	add.s32 	%r80, %r69, %r68;
	// inline asm
	mov.u32 	%r70, %ntid.x;
	// inline asm
	mul.lo.s32 	%r12, %r70, %r79;
	// inline asm
	mov.u32 	%r71, %ntid.y;
	// inline asm
	mul.lo.s32 	%r13, %r71, %r80;
	add.s32 	%r81, %r6, -1;
	shr.u32 	%r82, %r81, 1;
	add.s32 	%r83, %r7, -1;
	shr.u32 	%r84, %r83, 1;
	sub.s32 	%r136, %r12, %r82;
	sub.s32 	%r137, %r13, %r84;
	// inline asm
	mov.u32 	%r72, %ntid.x;
	// inline asm
	add.s32 	%r15, %r81, %r72;
	// inline asm
	mov.u32 	%r73, %ntid.y;
	// inline asm
	add.s32 	%r85, %r83, %r73;
	// inline asm
	mov.u32 	%r74, %tid.y;
	// inline asm
	// inline asm
	mov.u32 	%r75, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r76, %tid.x;
	// inline asm
	mad.lo.s32 	%r170, %r75, %r74, %r76;
	mul.lo.s32 	%r17, %r85, %r15;
	// inline asm
	mov.u32 	%r77, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r78, %ntid.y;
	// inline asm
	mul.lo.s32 	%r18, %r78, %r77;
	setp.ge.s32 	%p5, %r170, %r17;
	@%p5 bra 	BB0_3;

	ld.param.u32 	%r148, [Convolve_param_2];
	add.s32 	%r19, %r148, -1;
	ld.param.u32 	%r150, [Convolve_param_3];
	add.s32 	%r20, %r150, -1;
	mov.u32 	%r171, %r170;

BB0_2:
	rem.s32 	%r98, %r171, %r15;
	mov.u32 	%r94, 0;
	div.s32 	%r99, %r171, %r15;
	add.s32 	%r134, %r136, %r98;
	add.s32 	%r135, %r137, %r99;
	// inline asm
	max.s32 	%r86, %r134, %r94;
	// inline asm
	// inline asm
	min.s32 	%r89, %r86, %r19;
	// inline asm
	// inline asm
	max.s32 	%r92, %r135, %r94;
	// inline asm
	// inline asm
	min.s32 	%r95, %r92, %r20;
	// inline asm
	ld.param.u32 	%r147, [Convolve_param_2];
	mad.lo.s32 	%r100, %r95, %r147, %r89;
	shl.b32 	%r101, %r100, 4;
	ld.param.u32 	%r143, [Convolve_param_0];
	add.s32 	%r102, %r143, %r101;
	shl.b32 	%r103, %r171, 4;
	ld.param.u32 	%r165, [Convolve_param_9];
	add.s32 	%r104, %r165, %r103;
	ld.global.v4.f32 	{%f164, %f165, %f166, %f167}, [%r102];
	st.shared.v4.f32 	[%r104], {%f164, %f165, %f166, %f167};
	add.s32 	%r171, %r171, %r18;
	setp.lt.s32 	%p6, %r171, %r17;
	@%p6 bra 	BB0_2;

BB0_3:
	ld.param.u32 	%r156, [Convolve_param_5];
	ld.param.u32 	%r160, [Convolve_param_6];
	mul.lo.s32 	%r23, %r160, %r156;
	setp.ge.u32 	%p7, %r170, %r23;
	@%p7 bra 	BB0_5;

BB0_4:
	shl.b32 	%r105, %r170, 2;
	ld.param.u32 	%r168, [Convolve_param_10];
	add.s32 	%r106, %r168, %r105;
	ld.param.u32 	%r151, [Convolve_param_4];
	add.s32 	%r107, %r151, %r105;
	ld.const.f32 	%f13, [%r107];
	st.shared.f32 	[%r106], %f13;
	add.s32 	%r170, %r170, %r18;
	setp.lt.u32 	%p8, %r170, %r23;
	@%p8 bra 	BB0_4;

BB0_5:
	bar.sync 	0;
	// inline asm
	mov.u32 	%r108, %tid.x;
	// inline asm
	add.s32 	%r26, %r108, %r12;
	// inline asm
	mov.u32 	%r109, %tid.y;
	// inline asm
	add.s32 	%r27, %r109, %r13;
	ld.param.u32 	%r146, [Convolve_param_2];
	setp.lt.u32 	%p9, %r26, %r146;
	ld.param.u32 	%r149, [Convolve_param_3];
	setp.lt.u32 	%p10, %r27, %r149;
	and.pred  	%p11, %p9, %p10;
	@%p11 bra 	BB0_7;

	ret;

BB0_7:
	ld.param.u32 	%r162, [Convolve_param_8];
	and.b32  	%r111, %r162, 8;
	setp.eq.s32 	%p1, %r111, 0;
	ld.param.u32 	%r161, [Convolve_param_7];
	setp.eq.s32 	%p12, %r161, 0;
	or.pred  	%p13, %p1, %p12;
	// inline asm
	mov.u32 	%r110, %tid.y;
	// inline asm
	ld.param.u32 	%r159, [Convolve_param_6];
	setp.eq.s32 	%p2, %r159, 0;
	@%p13 bra 	BB0_20;

	@%p2 bra 	BB0_15;

	ld.param.u32 	%r152, [Convolve_param_5];
	setp.eq.s32 	%p3, %r152, 0;
	mov.u32 	%r174, 0;
	add.s32 	%r114, %r72, %r152;
	add.s32 	%r29, %r114, -1;
	mul.lo.s32 	%r172, %r110, %r29;
	mov.f32 	%f168, 0f00000000;
	mov.f32 	%f175, %f168;
	mov.f32 	%f176, %f168;
	mov.f32 	%f177, %f168;
	mov.f32 	%f178, %f168;
	mov.u32 	%r173, %r174;

BB0_10:
	// inline asm
	mov.u32 	%r115, %tid.x;
	// inline asm
	@%p3 bra 	BB0_14;

	add.s32 	%r117, %r115, %r172;
	shl.b32 	%r118, %r117, 4;
	ld.param.u32 	%r164, [Convolve_param_9];
	add.s32 	%r176, %r164, %r118;
	shl.b32 	%r119, %r174, 2;
	ld.param.u32 	%r167, [Convolve_param_10];
	add.s32 	%r175, %r167, %r119;
	mov.u32 	%r177, 0;

BB0_12:
	ld.shared.v4.f32 	{%f156, %f157, %f158, %f159}, [%r176];
	mov.f32 	%f16, 0f477FFF00;
	sub.f32 	%f17, %f16, %f159;
	mul.f32 	%f18, %f17, 0f377BA882;
	ld.shared.f32 	%f19, [%r175];
	mul.f32 	%f20, %f18, %f19;
	mad.f32 	%f23, %f20, %f156, %f175;
	mad.f32 	%f26, %f20, %f157, %f176;
	mad.f32 	%f29, %f20, %f158, %f177;
	mad.f32 	%f31, %f19, %f159, %f178;
	mov.f32 	%f175, %f23;
	mov.f32 	%f176, %f26;
	mov.f32 	%f177, %f29;
	mov.f32 	%f178, %f31;
	mad.f32 	%f168, %f18, %f19, %f168;
	add.s32 	%r176, %r176, 16;
	add.s32 	%r175, %r175, 4;
	add.s32 	%r177, %r177, 1;
	ld.param.u32 	%r155, [Convolve_param_5];
	setp.lt.u32 	%p14, %r177, %r155;
	@%p14 bra 	BB0_12;

	add.s32 	%r174, %r174, %r177;

BB0_14:
	add.s32 	%r173, %r173, 1;
	ld.param.u32 	%r158, [Convolve_param_6];
	setp.lt.u32 	%p15, %r173, %r158;
	add.s32 	%r172, %r172, %r29;
	@%p15 bra 	BB0_10;
	bra.uni 	BB0_16;

BB0_15:
	mov.f32 	%f168, 0f00000000;
	mov.f32 	%f175, %f168;
	mov.f32 	%f176, %f168;
	mov.f32 	%f177, %f168;
	mov.f32 	%f178, %f168;

BB0_16:
	setp.lt.f32 	%p16, %f168, 0f00000000;
	selp.f32 	%f6, 0fBF800000, 0f3F800000, %p16;
	mul.f32 	%f33, %f6, %f168;
	setp.ltu.f32 	%p17, %f33, 0f00000000;
	@%p17 bra 	BB0_18;

	rcp.approx.f32 	%f169, %f168;
	bra.uni 	BB0_19;

BB0_18:
	mul.f32 	%f169, %f6, 0f7F800000;

BB0_19:
	mul.f32 	%f128, %f169, %f175;
	mul.f32 	%f129, %f169, %f176;
	mul.f32 	%f130, %f169, %f177;
	mov.f32 	%f171, %f128;
	mov.f32 	%f172, %f129;
	mov.f32 	%f173, %f130;
	mov.f32 	%f174, %f178;
	bra.uni 	BB0_28;

BB0_20:
	@%p2 bra 	BB0_27;

	ld.param.u32 	%r153, [Convolve_param_5];
	setp.eq.s32 	%p4, %r153, 0;
	mov.u32 	%r180, 0;
	add.s32 	%r122, %r72, %r153;
	add.s32 	%r47, %r122, -1;
	mul.lo.s32 	%r178, %r110, %r47;
	mov.f32 	%f37, 0f00000000;
	mov.f32 	%f171, %f37;
	mov.f32 	%f172, %f37;
	mov.f32 	%f173, %f37;
	mov.f32 	%f174, %f37;
	mov.u32 	%r179, %r180;

BB0_22:
	// inline asm
	mov.u32 	%r123, %tid.x;
	// inline asm
	@%p4 bra 	BB0_26;

	add.s32 	%r125, %r123, %r178;
	shl.b32 	%r126, %r125, 4;
	ld.param.u32 	%r163, [Convolve_param_9];
	add.s32 	%r182, %r163, %r126;
	shl.b32 	%r127, %r180, 2;
	ld.param.u32 	%r166, [Convolve_param_10];
	add.s32 	%r181, %r166, %r127;
	mov.u32 	%r183, 0;

BB0_24:
	ld.shared.v4.f32 	{%f108, %f109, %f110, %f111}, [%r182];
	ld.shared.f32 	%f39, [%r181];
	mad.f32 	%f41, %f39, %f108, %f171;
	mad.f32 	%f44, %f39, %f109, %f172;
	mad.f32 	%f47, %f39, %f110, %f173;
	mad.f32 	%f50, %f39, %f111, %f174;
	mov.f32 	%f171, %f41;
	mov.f32 	%f172, %f44;
	mov.f32 	%f173, %f47;
	mov.f32 	%f174, %f50;
	add.s32 	%r182, %r182, 16;
	add.s32 	%r181, %r181, 4;
	add.s32 	%r183, %r183, 1;
	ld.param.u32 	%r154, [Convolve_param_5];
	setp.lt.u32 	%p18, %r183, %r154;
	@%p18 bra 	BB0_24;

	add.s32 	%r180, %r180, %r183;

BB0_26:
	add.s32 	%r179, %r179, 1;
	ld.param.u32 	%r157, [Convolve_param_6];
	setp.lt.u32 	%p19, %r179, %r157;
	add.s32 	%r178, %r178, %r47;
	@%p19 bra 	BB0_22;
	bra.uni 	BB0_28;

BB0_27:
	mov.f32 	%f51, 0f00000000;
	mov.f32 	%f171, %f51;
	mov.f32 	%f172, %f51;
	mov.f32 	%f173, %f51;
	mov.f32 	%f174, %f51;

BB0_28:
	mov.f32 	%f53, 0f00000000;
	max.f32 	%f54, %f171, %f53;
	mov.f32 	%f55, 0f477FFF00;
	min.f32 	%f56, %f54, %f55;
	add.f32 	%f57, %f56, 0f3F000000;
	max.f32 	%f59, %f172, %f53;
	min.f32 	%f60, %f59, %f55;
	add.f32 	%f61, %f60, 0f3F000000;
	max.f32 	%f63, %f173, %f53;
	min.f32 	%f64, %f63, %f55;
	add.f32 	%f65, %f64, 0f3F000000;
	ld.param.u32 	%r145, [Convolve_param_2];
	mad.lo.s32 	%r65, %r27, %r145, %r26;
	@%p1 bra 	BB0_30;

	max.f32 	%f69, %f174, %f53;
	min.f32 	%f71, %f69, %f55;
	add.f32 	%f170, %f71, 0f3F000000;
	bra.uni 	BB0_31;

BB0_30:
	shl.b32 	%r128, %r65, 4;
	ld.param.u32 	%r142, [Convolve_param_0];
	add.s32 	%r129, %r142, %r128;
	ld.global.f32 	%f170, [%r129+12];

BB0_31:
	shl.b32 	%r130, %r65, 4;
	ld.param.u32 	%r144, [Convolve_param_1];
	add.s32 	%r131, %r144, %r130;
	st.global.v4.f32 	[%r131], {%f57, %f61, %f65, %f170};
	ret;
}

.entry FunctionImage(
	.param .u32 .ptr .global .align 16 FunctionImage_param_0,
	.param .u32 FunctionImage_param_1,
	.param .u32 FunctionImage_param_2,
	.param .u32 FunctionImage_param_3,
	.param .u32 .ptr .const .align 4 FunctionImage_param_4
)
{
	.local .align 4 .b8 	__local_depot1[28];
	.reg .b32 	%SP;
	.reg .f32 	%f<899>;
	.reg .pred 	%p<120>;
	.reg .s32 	%r<642>;


	mov.u32 	%SP, __local_depot1;
	ld.param.u32 	%r172, [FunctionImage_param_0];
	ld.param.u32 	%r1, [FunctionImage_param_2];
	// inline asm
	mov.u32 	%r162, %envreg3;
	// inline asm
	// inline asm
	mov.u32 	%r163, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r164, %ctaid.x;
	// inline asm
	// inline asm
	mov.u32 	%r165, %tid.x;
	// inline asm
	// inline asm
	mov.u32 	%r166, %envreg4;
	// inline asm
	// inline asm
	mov.u32 	%r167, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r168, %ctaid.y;
	// inline asm
	// inline asm
	mov.u32 	%r169, %tid.y;
	// inline asm
	add.s32 	%r173, %r169, %r166;
	mad.lo.s32 	%r174, %r168, %r167, %r173;
	// inline asm
	mov.u32 	%r170, %envreg6;
	// inline asm
	// inline asm
	mov.u32 	%r171, %ntid.x;
	// inline asm
	mul.lo.s32 	%r175, %r174, %r170;
	mad.lo.s32 	%r176, %r164, %r163, %r162;
	add.s32 	%r177, %r176, %r165;
	mad.lo.s32 	%r178, %r175, %r171, %r177;
	shl.b32 	%r179, %r178, 4;
	add.s32 	%r4, %r172, %r179;
	ld.global.v4.f32 	{%f586, %f587, %f588, %f589}, [%r4];
	setp.gt.s32 	%p5, %r1, 2;
	@%p5 bra 	BB1_5;

	ld.param.u32 	%r566, [FunctionImage_param_2];
	setp.eq.s32 	%p8, %r566, 1;
	@%p8 bra 	BB1_154;

	ld.param.u32 	%r565, [FunctionImage_param_2];
	setp.eq.s32 	%p9, %r565, 2;
	@%p9 bra 	BB1_3;
	bra.uni 	BB1_158;

BB1_3:
	ld.param.u32 	%r574, [FunctionImage_param_3];
	setp.eq.s32 	%p30, %r574, 0;
	@%p30 bra 	BB1_59;

	ld.param.u32 	%r587, [FunctionImage_param_4];
	ld.const.f32 	%f337, [%r587];
	mul.f32 	%f875, %f337, 0f377BA882;
	bra.uni 	BB1_60;

BB1_5:
	ld.param.u32 	%r568, [FunctionImage_param_2];
	setp.eq.s32 	%p6, %r568, 3;
	@%p6 bra 	BB1_28;

	ld.param.u32 	%r567, [FunctionImage_param_2];
	setp.ne.s32 	%p7, %r567, 4;
	@%p7 bra 	BB1_158;

	ld.param.u32 	%r582, [FunctionImage_param_3];
	setp.eq.s32 	%p10, %r582, 0;
	@%p10 bra 	BB1_9;

	ld.param.u32 	%r595, [FunctionImage_param_4];
	ld.const.f32 	%f854, [%r595];
	bra.uni 	BB1_10;

BB1_9:
	mov.f32 	%f854, 0f3F800000;

BB1_10:
	ld.param.u32 	%r581, [FunctionImage_param_3];
	setp.gt.u32 	%p11, %r581, 1;
	@%p11 bra 	BB1_12;

	mov.f32 	%f855, 0f3F000000;
	bra.uni 	BB1_13;

BB1_12:
	ld.param.u32 	%r594, [FunctionImage_param_4];
	ld.const.f32 	%f855, [%r594+4];

BB1_13:
	ld.param.u32 	%r580, [FunctionImage_param_3];
	setp.gt.u32 	%p12, %r580, 2;
	@%p12 bra 	BB1_15;

	mov.f32 	%f856, 0f3F800000;
	bra.uni 	BB1_16;

BB1_15:
	ld.param.u32 	%r593, [FunctionImage_param_4];
	ld.const.f32 	%f856, [%r593+8];

BB1_16:
	ld.param.u32 	%r579, [FunctionImage_param_3];
	setp.gt.u32 	%p13, %r579, 3;
	@%p13 bra 	BB1_18;

	mov.f32 	%f857, 0f3F000000;
	bra.uni 	BB1_19;

BB1_18:
	ld.param.u32 	%r592, [FunctionImage_param_4];
	ld.const.f32 	%f857, [%r592+12];

BB1_19:
	mul.f32 	%f111, %f854, 0f40490FDC;
	mov.f32 	%f118, 0f377BA882;
	neg.f32 	%f838, %f855;
	mad.f32 	%f842, %f586, %f118, %f838;
	mad.f32 	%f843, %f587, %f118, %f838;
	mad.f32 	%f844, %f588, %f118, %f838;
	mad.f32 	%f845, %f589, %f118, %f838;
	mul.f32 	%f802, %f111, %f842;
	mul.f32 	%f803, %f111, %f843;
	mul.f32 	%f804, %f111, %f844;
	mul.f32 	%f805, %f111, %f845;
	div.full.f32 	%f119, %f856, 0f40490FDC;
	// inline asm
	abs.f32 	%f109, %f802;
	// inline asm
	setp.gt.f32 	%p1, %f109, 0f3F800000;
	mov.f32 	%f858, %f109;
	@%p1 bra 	BB1_20;
	bra.uni 	BB1_21;

BB1_20:
	rcp.approx.f32 	%f858, %f109;

BB1_21:
	mul.rn.f32 	%f125, %f858, %f858;
	mov.f32 	%f126, 0fBF52C7EA;
	mul.rn.f32 	%f127, %f125, %f126;
	add.f32 	%f128, %f127, 0fC0B59883;
	mul.rn.f32 	%f129, %f128, %f125;
	add.f32 	%f130, %f129, 0fC0D21907;
	mul.rn.f32 	%f131, %f130, %f125;
	mul.rn.f32 	%f132, %f131, %f858;
	add.f32 	%f133, %f125, 0f41355DC0;
	mul.rn.f32 	%f134, %f133, %f125;
	add.f32 	%f135, %f134, 0f41E6BD60;
	mul.rn.f32 	%f136, %f135, %f125;
	add.f32 	%f137, %f136, 0f419D92C8;
	rcp.approx.f32 	%f138, %f137;
	mul.rn.f32 	%f139, %f132, %f138;
	add.f32 	%f140, %f139, %f858;
	mov.f32 	%f141, 0f3FC90FDB;
	sub.f32 	%f142, %f141, %f140;
	selp.f32 	%f143, %f142, %f140, %p1;
	mov.b32 	 %r180, %f802;
	and.b32  	%r181, %r180, -2147483648;
	mov.b32 	 %r182, %f143;
	and.b32  	%r183, %r182, 2147483647;
	or.b32  	%r184, %r183, %r181;
	mov.b32 	 %f144, %r184;
	// inline asm
	abs.f32 	%f123, %f803;
	// inline asm
	setp.gt.f32 	%p2, %f123, 0f3F800000;
	mov.f32 	%f859, %f123;
	@%p2 bra 	BB1_22;
	bra.uni 	BB1_23;

BB1_22:
	rcp.approx.f32 	%f859, %f123;

BB1_23:
	mul.rn.f32 	%f150, %f859, %f859;
	mul.rn.f32 	%f152, %f150, %f126;
	add.f32 	%f153, %f152, 0fC0B59883;
	mul.rn.f32 	%f154, %f153, %f150;
	add.f32 	%f155, %f154, 0fC0D21907;
	mul.rn.f32 	%f156, %f155, %f150;
	mul.rn.f32 	%f157, %f156, %f859;
	add.f32 	%f158, %f150, 0f41355DC0;
	mul.rn.f32 	%f159, %f158, %f150;
	add.f32 	%f160, %f159, 0f41E6BD60;
	mul.rn.f32 	%f161, %f160, %f150;
	add.f32 	%f162, %f161, 0f419D92C8;
	rcp.approx.f32 	%f163, %f162;
	mul.rn.f32 	%f164, %f157, %f163;
	add.f32 	%f165, %f164, %f859;
	sub.f32 	%f167, %f141, %f165;
	selp.f32 	%f168, %f167, %f165, %p2;
	mov.b32 	 %r185, %f803;
	and.b32  	%r186, %r185, -2147483648;
	mov.b32 	 %r187, %f168;
	and.b32  	%r188, %r187, 2147483647;
	or.b32  	%r189, %r188, %r186;
	mov.b32 	 %f169, %r189;
	// inline asm
	abs.f32 	%f148, %f804;
	// inline asm
	setp.gt.f32 	%p3, %f148, 0f3F800000;
	mov.f32 	%f860, %f148;
	@%p3 bra 	BB1_24;
	bra.uni 	BB1_25;

BB1_24:
	rcp.approx.f32 	%f860, %f148;

BB1_25:
	mul.rn.f32 	%f172, %f860, %f860;
	mul.rn.f32 	%f174, %f172, %f126;
	add.f32 	%f175, %f174, 0fC0B59883;
	mul.rn.f32 	%f176, %f175, %f172;
	add.f32 	%f177, %f176, 0fC0D21907;
	mul.rn.f32 	%f178, %f177, %f172;
	mul.rn.f32 	%f179, %f178, %f860;
	add.f32 	%f180, %f172, 0f41355DC0;
	mul.rn.f32 	%f181, %f180, %f172;
	add.f32 	%f182, %f181, 0f41E6BD60;
	mul.rn.f32 	%f183, %f182, %f172;
	add.f32 	%f184, %f183, 0f419D92C8;
	rcp.approx.f32 	%f185, %f184;
	mul.rn.f32 	%f186, %f179, %f185;
	add.f32 	%f187, %f186, %f860;
	sub.f32 	%f189, %f141, %f187;
	selp.f32 	%f190, %f189, %f187, %p3;
	mov.b32 	 %r190, %f804;
	and.b32  	%r191, %r190, -2147483648;
	mov.b32 	 %r192, %f190;
	and.b32  	%r193, %r192, 2147483647;
	or.b32  	%r194, %r193, %r191;
	mov.b32 	 %f191, %r194;
	// inline asm
	abs.f32 	%f170, %f805;
	// inline asm
	setp.gt.f32 	%p4, %f170, 0f3F800000;
	mov.f32 	%f861, %f170;
	@%p4 bra 	BB1_26;
	bra.uni 	BB1_27;

BB1_26:
	rcp.approx.f32 	%f861, %f170;

BB1_27:
	mul.rn.f32 	%f192, %f861, %f861;
	mul.rn.f32 	%f194, %f192, %f126;
	add.f32 	%f195, %f194, 0fC0B59883;
	mul.rn.f32 	%f196, %f195, %f192;
	add.f32 	%f197, %f196, 0fC0D21907;
	mul.rn.f32 	%f198, %f197, %f192;
	mul.rn.f32 	%f199, %f198, %f861;
	add.f32 	%f200, %f192, 0f41355DC0;
	mul.rn.f32 	%f201, %f200, %f192;
	add.f32 	%f202, %f201, 0f41E6BD60;
	mul.rn.f32 	%f203, %f202, %f192;
	add.f32 	%f204, %f203, 0f419D92C8;
	rcp.approx.f32 	%f205, %f204;
	mul.rn.f32 	%f206, %f199, %f205;
	add.f32 	%f207, %f206, %f861;
	sub.f32 	%f209, %f141, %f207;
	selp.f32 	%f210, %f209, %f207, %p4;
	mov.b32 	 %r195, %f805;
	and.b32  	%r196, %r195, -2147483648;
	mov.b32 	 %r197, %f210;
	and.b32  	%r198, %r197, 2147483647;
	or.b32  	%r199, %r198, %r196;
	mov.b32 	 %f211, %r199;
	mad.f32 	%f786, %f119, %f144, %f857;
	mad.f32 	%f787, %f119, %f169, %f857;
	mad.f32 	%f788, %f119, %f191, %f857;
	mad.f32 	%f789, %f119, %f211, %f857;
	mov.f32 	%f215, 0f477FFF00;
	mul.f32 	%f891, %f786, %f215;
	mul.f32 	%f892, %f787, %f215;
	mul.f32 	%f893, %f788, %f215;
	mul.f32 	%f894, %f789, %f215;
	bra.uni 	BB1_159;

BB1_28:
	ld.param.u32 	%r578, [FunctionImage_param_3];
	setp.eq.s32 	%p14, %r578, 0;
	@%p14 bra 	BB1_30;

	ld.param.u32 	%r591, [FunctionImage_param_4];
	ld.const.f32 	%f862, [%r591];
	bra.uni 	BB1_31;

BB1_30:
	mov.f32 	%f862, 0f3F800000;

BB1_31:
	ld.param.u32 	%r577, [FunctionImage_param_3];
	setp.gt.u32 	%p15, %r577, 1;
	@%p15 bra 	BB1_33;

	mov.f32 	%f863, 0f3F000000;
	bra.uni 	BB1_34;

BB1_33:
	ld.param.u32 	%r590, [FunctionImage_param_4];
	ld.const.f32 	%f863, [%r590+4];

BB1_34:
	ld.param.u32 	%r576, [FunctionImage_param_3];
	setp.gt.u32 	%p16, %r576, 2;
	@%p16 bra 	BB1_36;

	mov.f32 	%f864, 0f3F800000;
	bra.uni 	BB1_37;

BB1_36:
	ld.param.u32 	%r589, [FunctionImage_param_4];
	ld.const.f32 	%f864, [%r589+8];

BB1_37:
	ld.param.u32 	%r575, [FunctionImage_param_3];
	setp.gt.u32 	%p17, %r575, 3;
	@%p17 bra 	BB1_39;

	mov.f32 	%f865, 0f3F000000;
	bra.uni 	BB1_40;

BB1_39:
	ld.param.u32 	%r588, [FunctionImage_param_4];
	ld.const.f32 	%f865, [%r588+12];

BB1_40:
	mov.f32 	%f236, 0f40000000;
	div.full.f32 	%f237, %f236, %f862;
	mov.f32 	%f244, 0f377BA882;
	neg.f32 	%f726, %f863;
	mad.f32 	%f730, %f586, %f244, %f726;
	mad.f32 	%f731, %f587, %f244, %f726;
	mad.f32 	%f732, %f588, %f244, %f726;
	mad.f32 	%f733, %f589, %f244, %f726;
	mul.f32 	%f734, %f237, %f730;
	mul.f32 	%f735, %f237, %f731;
	mul.f32 	%f736, %f237, %f732;
	mul.f32 	%f737, %f237, %f733;
	div.full.f32 	%f245, %f864, 0f40490FDC;
	// inline asm
	abs.f32 	%f220, %f734;
	// inline asm
	mov.f32 	%f249, 0f3F800000;
	sub.f32 	%f250, %f249, %f220;
	mov.f32 	%f251, 0f3F000000;
	mul.rn.f32 	%f223, %f251, %f250;
	// inline asm
	sqrt.approx.f32 	%f222, %f223;
	// inline asm
	setp.gt.f32 	%p18, %f220, 0f3F133333;
	selp.f32 	%f252, %f222, %f220, %p18;
	mul.rn.f32 	%f253, %f252, %f252;
	mov.f32 	%f254, 0fBF004C2C;
	mul.rn.f32 	%f255, %f254, %f253;
	add.f32 	%f256, %f255, 0f3F6A4AA5;
	mul.rn.f32 	%f257, %f256, %f253;
	mul.rn.f32 	%f258, %f257, %f252;
	add.f32 	%f259, %f253, 0fC0AF5123;
	mul.rn.f32 	%f260, %f259, %f253;
	add.f32 	%f261, %f260, 0f40AFB829;
	rcp.approx.f32 	%f262, %f261;
	mul.rn.f32 	%f263, %f258, %f262;
	add.f32 	%f264, %f263, %f252;
	mov.f32 	%f265, 0fC0000000;
	mul.rn.f32 	%f266, %f265, %f264;
	add.f32 	%f267, %f266, 0f3FC90FDB;
	selp.f32 	%f268, %f267, %f264, %p18;
	mov.b32 	 %r200, %f734;
	and.b32  	%r201, %r200, -2147483648;
	mov.b32 	 %r202, %f268;
	and.b32  	%r203, %r202, 2147483647;
	or.b32  	%r204, %r203, %r201;
	mov.b32 	 %f269, %r204;
	// inline asm
	abs.f32 	%f224, %f735;
	// inline asm
	sub.f32 	%f270, %f249, %f224;
	mul.rn.f32 	%f227, %f251, %f270;
	// inline asm
	sqrt.approx.f32 	%f226, %f227;
	// inline asm
	setp.gt.f32 	%p19, %f224, 0f3F133333;
	selp.f32 	%f271, %f226, %f224, %p19;
	mul.rn.f32 	%f272, %f271, %f271;
	mul.rn.f32 	%f273, %f254, %f272;
	add.f32 	%f274, %f273, 0f3F6A4AA5;
	mul.rn.f32 	%f275, %f274, %f272;
	mul.rn.f32 	%f276, %f275, %f271;
	add.f32 	%f277, %f272, 0fC0AF5123;
	mul.rn.f32 	%f278, %f277, %f272;
	add.f32 	%f279, %f278, 0f40AFB829;
	rcp.approx.f32 	%f280, %f279;
	mul.rn.f32 	%f281, %f276, %f280;
	add.f32 	%f282, %f281, %f271;
	mul.rn.f32 	%f283, %f265, %f282;
	add.f32 	%f284, %f283, 0f3FC90FDB;
	selp.f32 	%f285, %f284, %f282, %p19;
	mov.b32 	 %r205, %f735;
	and.b32  	%r206, %r205, -2147483648;
	mov.b32 	 %r207, %f285;
	and.b32  	%r208, %r207, 2147483647;
	or.b32  	%r209, %r208, %r206;
	mov.b32 	 %f286, %r209;
	// inline asm
	abs.f32 	%f228, %f736;
	// inline asm
	sub.f32 	%f287, %f249, %f228;
	mul.rn.f32 	%f231, %f251, %f287;
	// inline asm
	sqrt.approx.f32 	%f230, %f231;
	// inline asm
	setp.gt.f32 	%p20, %f228, 0f3F133333;
	selp.f32 	%f288, %f230, %f228, %p20;
	mul.rn.f32 	%f289, %f288, %f288;
	mul.rn.f32 	%f290, %f254, %f289;
	add.f32 	%f291, %f290, 0f3F6A4AA5;
	mul.rn.f32 	%f292, %f291, %f289;
	mul.rn.f32 	%f293, %f292, %f288;
	add.f32 	%f294, %f289, 0fC0AF5123;
	mul.rn.f32 	%f295, %f294, %f289;
	add.f32 	%f296, %f295, 0f40AFB829;
	rcp.approx.f32 	%f297, %f296;
	mul.rn.f32 	%f298, %f293, %f297;
	add.f32 	%f299, %f298, %f288;
	mul.rn.f32 	%f300, %f265, %f299;
	add.f32 	%f301, %f300, 0f3FC90FDB;
	selp.f32 	%f302, %f301, %f299, %p20;
	mov.b32 	 %r210, %f736;
	and.b32  	%r211, %r210, -2147483648;
	mov.b32 	 %r212, %f302;
	and.b32  	%r213, %r212, 2147483647;
	or.b32  	%r214, %r213, %r211;
	mov.b32 	 %f303, %r214;
	// inline asm
	abs.f32 	%f232, %f737;
	// inline asm
	sub.f32 	%f304, %f249, %f232;
	mul.rn.f32 	%f235, %f251, %f304;
	// inline asm
	sqrt.approx.f32 	%f234, %f235;
	// inline asm
	setp.gt.f32 	%p21, %f232, 0f3F133333;
	selp.f32 	%f305, %f234, %f232, %p21;
	mul.rn.f32 	%f306, %f305, %f305;
	mul.rn.f32 	%f307, %f254, %f306;
	add.f32 	%f308, %f307, 0f3F6A4AA5;
	mul.rn.f32 	%f309, %f308, %f306;
	mul.rn.f32 	%f310, %f309, %f305;
	add.f32 	%f311, %f306, 0fC0AF5123;
	mul.rn.f32 	%f312, %f311, %f306;
	add.f32 	%f313, %f312, 0f40AFB829;
	rcp.approx.f32 	%f314, %f313;
	mul.rn.f32 	%f315, %f310, %f314;
	add.f32 	%f316, %f315, %f305;
	mul.rn.f32 	%f317, %f265, %f316;
	add.f32 	%f318, %f317, 0f3FC90FDB;
	selp.f32 	%f319, %f318, %f316, %p21;
	mov.b32 	 %r215, %f737;
	and.b32  	%r216, %r215, -2147483648;
	mov.b32 	 %r217, %f319;
	and.b32  	%r218, %r217, 2147483647;
	or.b32  	%r219, %r218, %r216;
	mov.b32 	 %f320, %r219;
	mad.f32 	%f690, %f245, %f269, %f865;
	mad.f32 	%f691, %f245, %f286, %f865;
	mad.f32 	%f692, %f245, %f303, %f865;
	mad.f32 	%f693, %f245, %f320, %f865;
	mov.f32 	%f873, %f690;
	setp.gtu.f32 	%p22, %f690, 0fBF800000;
	@%p22 bra 	BB1_42;

	div.full.f32 	%f324, %f864, 0fC0000000;
	add.f32 	%f873, %f865, %f324;

BB1_42:
	mov.f32 	%f872, %f873;
	setp.ltu.f32 	%p23, %f872, 0f3F800000;
	@%p23 bra 	BB1_44;

	div.full.f32 	%f325, %f864, 0f40000000;
	add.f32 	%f872, %f865, %f325;

BB1_44:
	mov.f32 	%f37, %f872;
	mov.f32 	%f866, %f691;
	setp.gtu.f32 	%p24, %f691, 0fBF800000;
	@%p24 bra 	BB1_46;

	div.full.f32 	%f329, %f864, 0fC0000000;
	add.f32 	%f866, %f865, %f329;

BB1_46:
	setp.ltu.f32 	%p25, %f866, 0f3F800000;
	@%p25 bra 	BB1_48;

	div.full.f32 	%f330, %f864, 0f40000000;
	add.f32 	%f866, %f865, %f330;

BB1_48:
	setp.gtu.f32 	%p26, %f692, 0fBF800000;
	@%p26 bra 	BB1_50;

	div.full.f32 	%f332, %f864, 0fC0000000;
	add.f32 	%f871, %f865, %f332;
	bra.uni 	BB1_51;

BB1_50:
	mov.f32 	%f871, %f37;

BB1_51:
	setp.ltu.f32 	%p27, %f871, 0f3F800000;
	@%p27 bra 	BB1_53;

	div.full.f32 	%f333, %f864, 0f40000000;
	add.f32 	%f45, %f865, %f333;
	mov.f32 	%f870, %f45;
	bra.uni 	BB1_54;

BB1_53:
	mov.f32 	%f870, %f37;

BB1_54:
	mov.f32 	%f46, %f870;
	mov.f32 	%f874, %f693;
	setp.gtu.f32 	%p28, %f693, 0fBF800000;
	@%p28 bra 	BB1_56;

	div.full.f32 	%f334, %f864, 0fC0000000;
	add.f32 	%f874, %f865, %f334;

BB1_56:
	setp.ltu.f32 	%p29, %f874, 0f3F800000;
	@%p29 bra 	BB1_58;

	div.full.f32 	%f335, %f864, 0f40000000;
	add.f32 	%f874, %f865, %f335;

BB1_58:
	mov.f32 	%f336, 0f477FFF00;
	mul.f32 	%f891, %f37, %f336;
	mul.f32 	%f892, %f866, %f336;
	mul.f32 	%f893, %f46, %f336;
	mul.f32 	%f894, %f874, %f336;
	bra.uni 	BB1_159;

BB1_59:
	mov.f32 	%f875, 0f377BA882;

BB1_60:
	ld.param.u32 	%r573, [FunctionImage_param_3];
	setp.gt.u32 	%p31, %r573, 1;
	@%p31 bra 	BB1_62;

	mov.f32 	%f876, 0f00000000;
	bra.uni 	BB1_63;

BB1_62:
	ld.param.u32 	%r586, [FunctionImage_param_4];
	ld.const.f32 	%f876, [%r586+4];

BB1_63:
	ld.param.u32 	%r572, [FunctionImage_param_3];
	setp.gt.u32 	%p32, %r572, 2;
	@%p32 bra 	BB1_65;

	mov.f32 	%f877, 0f3F000000;
	bra.uni 	BB1_66;

BB1_65:
	ld.param.u32 	%r585, [FunctionImage_param_4];
	ld.const.f32 	%f877, [%r585+8];

BB1_66:
	ld.param.u32 	%r571, [FunctionImage_param_3];
	setp.gt.u32 	%p33, %r571, 3;
	@%p33 bra 	BB1_68;

	mov.f32 	%f878, 0f3F000000;
	bra.uni 	BB1_69;

BB1_68:
	ld.param.u32 	%r584, [FunctionImage_param_4];
	ld.const.f32 	%f878, [%r584+12];

BB1_69:
	div.full.f32 	%f348, %f876, 0f43B40000;
	mad.f32 	%f666, %f875, %f586, %f348;
	mad.f32 	%f667, %f875, %f587, %f348;
	mad.f32 	%f668, %f875, %f588, %f348;
	mad.f32 	%f669, %f875, %f589, %f348;
	mov.f32 	%f352, 0f40C90FDC;
	mul.f32 	%f626, %f666, %f352;
	mul.f32 	%f627, %f667, %f352;
	mul.f32 	%f628, %f668, %f352;
	mul.f32 	%f629, %f669, %f352;
	mov.f32 	%f61, 0f7F800000;
	setp.eq.f32 	%p34, %f626, 0f7F800000;
	add.u32 	%r5, %SP, 0;
	@%p34 bra 	BB1_89;

	setp.eq.f32 	%p35, %f626, 0fFF800000;
	setp.eq.f32 	%p36, %f626, 0f00000000;
	or.pred  	%p37, %p35, %p36;
	@%p37 bra 	BB1_89;

	// inline asm
	abs.f32 	%f353, %f626;
	// inline asm
	setp.gt.f32 	%p38, %f353, 0f473BA700;
	@%p38 bra 	BB1_73;

	mov.f32 	%f357, 0f3F22F983;
	mul.rn.f32 	%f356, %f626, %f357;
	// inline asm
	cvt.rni.f32.f32 	%f355, %f356;
	// inline asm
	cvt.rzi.s32.f32 	%r606, %f355;
	cvt.rn.f32.s32 	%f358, %r606;
	mov.f32 	%f359, 0f3FC90000;
	mul.rn.f32 	%f360, %f358, %f359;
	sub.f32 	%f361, %f626, %f360;
	mov.f32 	%f362, 0f39FD8000;
	mul.rn.f32 	%f363, %f358, %f362;
	sub.f32 	%f364, %f361, %f363;
	mov.f32 	%f365, 0f34A88000;
	mul.rn.f32 	%f366, %f358, %f365;
	sub.f32 	%f367, %f364, %f366;
	mov.f32 	%f368, 0f2E85A309;
	mul.rn.f32 	%f369, %f358, %f368;
	sub.f32 	%f879, %f367, %f369;
	bra.uni 	BB1_85;

BB1_73:
	mov.b32 	 %r7, %f626;
	and.b32  	%r598, %r7, -2147483648;
	shr.u32 	%r9, %r7, 23;
	and.b32  	%r238, %r9, 255;
	add.s32 	%r239, %r238, -128;
	shl.b32 	%r240, %r7, 8;
	or.b32  	%r237, %r240, -2147483648;
	shr.u32 	%r241, %r239, 5;
	mov.u32 	%r242, 4;
	sub.s32 	%r243, %r242, %r241;
	ld.const.u32 	%r221, [__GPU_i2opi_f];
	mul.lo.s32 	%r244, %r221, %r237;
	// inline asm
	mul.hi.u32 	%r220, %r221, %r237;
	// inline asm
	st.local.u32 	[%r5], %r244;
	ld.const.u32 	%r224, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r245, %r224, %r237;
	// inline asm
	mul.hi.u32 	%r223, %r224, %r237;
	// inline asm
	mad.lo.s32 	%r246, %r224, %r237, %r220;
	setp.lt.u32 	%p39, %r246, %r245;
	selp.u32 	%r247, 1, 0, %p39;
	add.s32 	%r248, %r247, %r223;
	st.local.u32 	[%r5+4], %r246;
	ld.const.u32 	%r227, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r249, %r227, %r237;
	// inline asm
	mul.hi.u32 	%r226, %r227, %r237;
	// inline asm
	mad.lo.s32 	%r250, %r227, %r237, %r248;
	setp.lt.u32 	%p40, %r250, %r249;
	selp.u32 	%r251, 1, 0, %p40;
	add.s32 	%r252, %r251, %r226;
	st.local.u32 	[%r5+8], %r250;
	ld.const.u32 	%r230, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r253, %r230, %r237;
	// inline asm
	mul.hi.u32 	%r229, %r230, %r237;
	// inline asm
	mad.lo.s32 	%r254, %r230, %r237, %r252;
	setp.lt.u32 	%p41, %r254, %r253;
	selp.u32 	%r255, 1, 0, %p41;
	add.s32 	%r256, %r255, %r229;
	st.local.u32 	[%r5+12], %r254;
	ld.const.u32 	%r233, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r257, %r233, %r237;
	// inline asm
	mul.hi.u32 	%r232, %r233, %r237;
	// inline asm
	mad.lo.s32 	%r258, %r233, %r237, %r256;
	setp.lt.u32 	%p42, %r258, %r257;
	selp.u32 	%r259, 1, 0, %p42;
	add.s32 	%r260, %r259, %r232;
	st.local.u32 	[%r5+16], %r258;
	ld.const.u32 	%r236, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r261, %r236, %r237;
	// inline asm
	mul.hi.u32 	%r235, %r236, %r237;
	// inline asm
	mad.lo.s32 	%r262, %r236, %r237, %r260;
	setp.lt.u32 	%p43, %r262, %r261;
	selp.u32 	%r263, 1, 0, %p43;
	add.s32 	%r264, %r263, %r235;
	st.local.u32 	[%r5+20], %r262;
	st.local.u32 	[%r5+24], %r264;
	and.b32  	%r10, %r9, 31;
	shl.b32 	%r266, %r243, 2;
	add.s32 	%r267, %r266, %r5;
	add.s32 	%r11, %r267, -16;
	ld.local.u32 	%r596, [%r267+8];
	ld.local.u32 	%r597, [%r267+4];
	setp.eq.s32 	%p44, %r10, 0;
	@%p44 bra 	BB1_75;

	shl.b32 	%r268, %r596, %r10;
	neg.s32 	%r269, %r9;
	and.b32  	%r270, %r269, 31;
	shr.u32 	%r271, %r597, %r270;
	or.b32  	%r596, %r271, %r268;
	ld.local.u32 	%r272, [%r11+16];
	shr.u32 	%r273, %r272, %r270;
	shl.b32 	%r274, %r597, %r10;
	or.b32  	%r597, %r273, %r274;

BB1_75:
	shr.u32 	%r275, %r597, 30;
	shl.b32 	%r276, %r596, 2;
	or.b32  	%r602, %r275, %r276;
	shl.b32 	%r19, %r597, 2;
	setp.ne.s32 	%p45, %r19, 0;
	selp.u32 	%r277, 1, 0, %p45;
	add.s32 	%r278, %r277, %r602;
	setp.gt.u32 	%p46, %r278, -2147483648;
	selp.u32 	%r279, 1, 0, %p46;
	shr.u32 	%r280, %r596, 30;
	add.s32 	%r281, %r279, %r280;
	neg.s32 	%r282, %r281;
	setp.lt.s32 	%p47, %r7, 0;
	selp.b32 	%r606, %r282, %r281, %p47;
	@%p46 bra 	BB1_77;

	mov.u32 	%r601, %r19;
	bra.uni 	BB1_78;

BB1_77:
	not.b32 	%r283, %r602;
	neg.s32 	%r21, %r19;
	setp.eq.s32 	%p48, %r19, 0;
	selp.u32 	%r284, 1, 0, %p48;
	add.s32 	%r602, %r284, %r283;
	xor.b32  	%r598, %r598, -2147483648;
	mov.u32 	%r601, %r21;

BB1_78:
	mov.u32 	%r600, %r601;
	setp.gt.s32 	%p49, %r602, 0;
	@%p49 bra 	BB1_80;

	mov.u32 	%r605, 0;
	bra.uni 	BB1_82;

BB1_80:
	mov.u32 	%r605, 0;

BB1_81:
	shr.u32 	%r287, %r600, 31;
	shl.b32 	%r288, %r602, 1;
	or.b32  	%r602, %r287, %r288;
	shl.b32 	%r600, %r600, 1;
	add.s32 	%r605, %r605, -1;
	setp.gt.s32 	%p50, %r602, 0;
	@%p50 bra 	BB1_81;

BB1_82:
	mul.lo.s32 	%r604, %r602, -921707870;
	mov.u32 	%r291, -921707870;
	// inline asm
	mul.hi.u32 	%r289, %r602, %r291;
	// inline asm
	setp.gt.s32 	%p51, %r289, 0;
	mov.u32 	%r603, %r289;
	@%p51 bra 	BB1_83;
	bra.uni 	BB1_84;

BB1_83:
	shl.b32 	%r292, %r289, 1;
	shr.u32 	%r293, %r604, 31;
	or.b32  	%r603, %r292, %r293;
	mul.lo.s32 	%r604, %r602, -1843415740;
	add.s32 	%r605, %r605, -1;

BB1_84:
	setp.ne.s32 	%p52, %r604, 0;
	selp.u32 	%r294, 1, 0, %p52;
	add.s32 	%r295, %r294, %r603;
	shr.u32 	%r296, %r295, 8;
	shr.u32 	%r297, %r295, 7;
	and.b32  	%r298, %r297, 1;
	shl.b32 	%r299, %r605, 23;
	add.s32 	%r300, %r299, %r296;
	add.s32 	%r301, %r300, %r298;
	add.s32 	%r302, %r301, 1056964608;
	or.b32  	%r303, %r302, %r598;
	mov.b32 	 %f879, %r303;

BB1_85:
	and.b32  	%r304, %r606, 1;
	setp.eq.s32 	%p53, %r304, 0;
	mul.rn.f32 	%f65, %f879, %f879;
	@%p53 bra 	BB1_87;

	mov.f32 	%f370, 0f37CCF5CE;
	mul.rn.f32 	%f371, %f370, %f65;
	add.f32 	%f372, %f371, 0fBAB6061A;
	mul.rn.f32 	%f373, %f372, %f65;
	add.f32 	%f374, %f373, 0f3D2AAAA5;
	mul.rn.f32 	%f375, %f374, %f65;
	add.f32 	%f376, %f375, 0fBF000000;
	mul.rn.f32 	%f377, %f376, %f65;
	add.f32 	%f880, %f377, 0f3F800000;
	bra.uni 	BB1_88;

BB1_87:
	mov.f32 	%f378, 0fB94CA1F9;
	mul.rn.f32 	%f379, %f378, %f65;
	add.f32 	%f380, %f379, 0f3C08839E;
	mul.rn.f32 	%f381, %f380, %f65;
	add.f32 	%f382, %f381, 0fBE2AAAA3;
	mul.rn.f32 	%f383, %f382, %f65;
	mul.rn.f32 	%f384, %f383, %f879;
	add.f32 	%f880, %f384, %f879;

BB1_88:
	and.b32  	%r305, %r606, 2;
	setp.eq.s32 	%p54, %r305, 0;
	neg.f32 	%f385, %f880;
	selp.f32 	%f881, %f880, %f385, %p54;
	bra.uni 	BB1_90;

BB1_89:
	mov.f32 	%f386, 0f00000000;
	mul.rn.f32 	%f881, %f626, %f386;

BB1_90:
	setp.eq.f32 	%p55, %f627, %f61;
	@%p55 bra 	BB1_110;

	setp.eq.f32 	%p56, %f627, 0fFF800000;
	setp.eq.f32 	%p57, %f627, 0f00000000;
	or.pred  	%p58, %p56, %p57;
	@%p58 bra 	BB1_110;

	// inline asm
	abs.f32 	%f390, %f627;
	// inline asm
	setp.gt.f32 	%p59, %f390, 0f473BA700;
	@%p59 bra 	BB1_94;

	mov.f32 	%f394, 0f3F22F983;
	mul.rn.f32 	%f393, %f627, %f394;
	// inline asm
	cvt.rni.f32.f32 	%f392, %f393;
	// inline asm
	cvt.rzi.s32.f32 	%r617, %f392;
	cvt.rn.f32.s32 	%f395, %r617;
	mov.f32 	%f396, 0f3FC90000;
	mul.rn.f32 	%f397, %f395, %f396;
	sub.f32 	%f398, %f627, %f397;
	mov.f32 	%f399, 0f39FD8000;
	mul.rn.f32 	%f400, %f395, %f399;
	sub.f32 	%f401, %f398, %f400;
	mov.f32 	%f402, 0f34A88000;
	mul.rn.f32 	%f403, %f395, %f402;
	sub.f32 	%f404, %f401, %f403;
	mov.f32 	%f405, 0f2E85A309;
	mul.rn.f32 	%f406, %f395, %f405;
	sub.f32 	%f882, %f404, %f406;
	bra.uni 	BB1_106;

BB1_94:
	mov.b32 	 %r45, %f627;
	and.b32  	%r609, %r45, -2147483648;
	shr.u32 	%r47, %r45, 23;
	and.b32  	%r324, %r47, 255;
	add.s32 	%r325, %r324, -128;
	shl.b32 	%r326, %r45, 8;
	or.b32  	%r323, %r326, -2147483648;
	shr.u32 	%r327, %r325, 5;
	mov.u32 	%r328, 4;
	sub.s32 	%r329, %r328, %r327;
	ld.const.u32 	%r307, [__GPU_i2opi_f];
	mul.lo.s32 	%r330, %r307, %r323;
	// inline asm
	mul.hi.u32 	%r306, %r307, %r323;
	// inline asm
	st.local.u32 	[%r5], %r330;
	ld.const.u32 	%r310, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r331, %r310, %r323;
	// inline asm
	mul.hi.u32 	%r309, %r310, %r323;
	// inline asm
	mad.lo.s32 	%r332, %r310, %r323, %r306;
	setp.lt.u32 	%p60, %r332, %r331;
	selp.u32 	%r333, 1, 0, %p60;
	add.s32 	%r334, %r333, %r309;
	st.local.u32 	[%r5+4], %r332;
	ld.const.u32 	%r313, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r335, %r313, %r323;
	// inline asm
	mul.hi.u32 	%r312, %r313, %r323;
	// inline asm
	mad.lo.s32 	%r336, %r313, %r323, %r334;
	setp.lt.u32 	%p61, %r336, %r335;
	selp.u32 	%r337, 1, 0, %p61;
	add.s32 	%r338, %r337, %r312;
	st.local.u32 	[%r5+8], %r336;
	ld.const.u32 	%r316, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r339, %r316, %r323;
	// inline asm
	mul.hi.u32 	%r315, %r316, %r323;
	// inline asm
	mad.lo.s32 	%r340, %r316, %r323, %r338;
	setp.lt.u32 	%p62, %r340, %r339;
	selp.u32 	%r341, 1, 0, %p62;
	add.s32 	%r342, %r341, %r315;
	st.local.u32 	[%r5+12], %r340;
	ld.const.u32 	%r319, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r343, %r319, %r323;
	// inline asm
	mul.hi.u32 	%r318, %r319, %r323;
	// inline asm
	mad.lo.s32 	%r344, %r319, %r323, %r342;
	setp.lt.u32 	%p63, %r344, %r343;
	selp.u32 	%r345, 1, 0, %p63;
	add.s32 	%r346, %r345, %r318;
	st.local.u32 	[%r5+16], %r344;
	ld.const.u32 	%r322, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r347, %r322, %r323;
	// inline asm
	mul.hi.u32 	%r321, %r322, %r323;
	// inline asm
	mad.lo.s32 	%r348, %r322, %r323, %r346;
	setp.lt.u32 	%p64, %r348, %r347;
	selp.u32 	%r349, 1, 0, %p64;
	add.s32 	%r350, %r349, %r321;
	st.local.u32 	[%r5+20], %r348;
	st.local.u32 	[%r5+24], %r350;
	and.b32  	%r48, %r47, 31;
	shl.b32 	%r352, %r329, 2;
	add.s32 	%r353, %r352, %r5;
	add.s32 	%r49, %r353, -16;
	ld.local.u32 	%r607, [%r353+8];
	ld.local.u32 	%r608, [%r353+4];
	setp.eq.s32 	%p65, %r48, 0;
	@%p65 bra 	BB1_96;

	shl.b32 	%r354, %r607, %r48;
	neg.s32 	%r355, %r47;
	and.b32  	%r356, %r355, 31;
	shr.u32 	%r357, %r608, %r356;
	or.b32  	%r607, %r357, %r354;
	ld.local.u32 	%r358, [%r49+16];
	shr.u32 	%r359, %r358, %r356;
	shl.b32 	%r360, %r608, %r48;
	or.b32  	%r608, %r359, %r360;

BB1_96:
	shr.u32 	%r361, %r608, 30;
	shl.b32 	%r362, %r607, 2;
	or.b32  	%r613, %r361, %r362;
	shl.b32 	%r57, %r608, 2;
	setp.ne.s32 	%p66, %r57, 0;
	selp.u32 	%r363, 1, 0, %p66;
	add.s32 	%r364, %r363, %r613;
	setp.gt.u32 	%p67, %r364, -2147483648;
	selp.u32 	%r365, 1, 0, %p67;
	shr.u32 	%r366, %r607, 30;
	add.s32 	%r367, %r365, %r366;
	neg.s32 	%r368, %r367;
	setp.lt.s32 	%p68, %r45, 0;
	selp.b32 	%r617, %r368, %r367, %p68;
	@%p67 bra 	BB1_98;

	mov.u32 	%r612, %r57;
	bra.uni 	BB1_99;

BB1_98:
	not.b32 	%r369, %r613;
	neg.s32 	%r59, %r57;
	setp.eq.s32 	%p69, %r57, 0;
	selp.u32 	%r370, 1, 0, %p69;
	add.s32 	%r613, %r370, %r369;
	xor.b32  	%r609, %r609, -2147483648;
	mov.u32 	%r612, %r59;

BB1_99:
	mov.u32 	%r611, %r612;
	setp.gt.s32 	%p70, %r613, 0;
	@%p70 bra 	BB1_101;

	mov.u32 	%r616, 0;
	bra.uni 	BB1_103;

BB1_101:
	mov.u32 	%r616, 0;

BB1_102:
	shr.u32 	%r373, %r611, 31;
	shl.b32 	%r374, %r613, 1;
	or.b32  	%r613, %r373, %r374;
	shl.b32 	%r611, %r611, 1;
	add.s32 	%r616, %r616, -1;
	setp.gt.s32 	%p71, %r613, 0;
	@%p71 bra 	BB1_102;

BB1_103:
	mul.lo.s32 	%r615, %r613, -921707870;
	mov.u32 	%r377, -921707870;
	// inline asm
	mul.hi.u32 	%r375, %r613, %r377;
	// inline asm
	setp.gt.s32 	%p72, %r375, 0;
	mov.u32 	%r614, %r375;
	@%p72 bra 	BB1_104;
	bra.uni 	BB1_105;

BB1_104:
	shl.b32 	%r378, %r375, 1;
	shr.u32 	%r379, %r615, 31;
	or.b32  	%r614, %r378, %r379;
	mul.lo.s32 	%r615, %r613, -1843415740;
	add.s32 	%r616, %r616, -1;

BB1_105:
	setp.ne.s32 	%p73, %r615, 0;
	selp.u32 	%r380, 1, 0, %p73;
	add.s32 	%r381, %r380, %r614;
	shr.u32 	%r382, %r381, 8;
	shr.u32 	%r383, %r381, 7;
	and.b32  	%r384, %r383, 1;
	shl.b32 	%r385, %r616, 23;
	add.s32 	%r386, %r385, %r382;
	add.s32 	%r387, %r386, %r384;
	add.s32 	%r388, %r387, 1056964608;
	or.b32  	%r389, %r388, %r609;
	mov.b32 	 %f882, %r389;

BB1_106:
	and.b32  	%r390, %r617, 1;
	setp.eq.s32 	%p74, %r390, 0;
	mul.rn.f32 	%f76, %f882, %f882;
	@%p74 bra 	BB1_108;

	mov.f32 	%f407, 0f37CCF5CE;
	mul.rn.f32 	%f408, %f407, %f76;
	add.f32 	%f409, %f408, 0fBAB6061A;
	mul.rn.f32 	%f410, %f409, %f76;
	add.f32 	%f411, %f410, 0f3D2AAAA5;
	mul.rn.f32 	%f412, %f411, %f76;
	add.f32 	%f413, %f412, 0fBF000000;
	mul.rn.f32 	%f414, %f413, %f76;
	add.f32 	%f883, %f414, 0f3F800000;
	bra.uni 	BB1_109;

BB1_108:
	mov.f32 	%f415, 0fB94CA1F9;
	mul.rn.f32 	%f416, %f415, %f76;
	add.f32 	%f417, %f416, 0f3C08839E;
	mul.rn.f32 	%f418, %f417, %f76;
	add.f32 	%f419, %f418, 0fBE2AAAA3;
	mul.rn.f32 	%f420, %f419, %f76;
	mul.rn.f32 	%f421, %f420, %f882;
	add.f32 	%f883, %f421, %f882;

BB1_109:
	and.b32  	%r391, %r617, 2;
	setp.eq.s32 	%p75, %r391, 0;
	neg.f32 	%f422, %f883;
	selp.f32 	%f884, %f883, %f422, %p75;
	bra.uni 	BB1_111;

BB1_110:
	mov.f32 	%f423, 0f00000000;
	mul.rn.f32 	%f884, %f627, %f423;

BB1_111:
	setp.eq.f32 	%p76, %f628, %f61;
	@%p76 bra 	BB1_131;

	setp.eq.f32 	%p77, %f628, 0fFF800000;
	setp.eq.f32 	%p78, %f628, 0f00000000;
	or.pred  	%p79, %p77, %p78;
	@%p79 bra 	BB1_131;

	// inline asm
	abs.f32 	%f424, %f628;
	// inline asm
	setp.gt.f32 	%p80, %f424, 0f473BA700;
	@%p80 bra 	BB1_115;

	mov.f32 	%f428, 0f3F22F983;
	mul.rn.f32 	%f427, %f628, %f428;
	// inline asm
	cvt.rni.f32.f32 	%f426, %f427;
	// inline asm
	cvt.rzi.s32.f32 	%r628, %f426;
	cvt.rn.f32.s32 	%f429, %r628;
	mov.f32 	%f430, 0f3FC90000;
	mul.rn.f32 	%f431, %f429, %f430;
	sub.f32 	%f432, %f628, %f431;
	mov.f32 	%f433, 0f39FD8000;
	mul.rn.f32 	%f434, %f429, %f433;
	sub.f32 	%f435, %f432, %f434;
	mov.f32 	%f436, 0f34A88000;
	mul.rn.f32 	%f437, %f429, %f436;
	sub.f32 	%f438, %f435, %f437;
	mov.f32 	%f439, 0f2E85A309;
	mul.rn.f32 	%f440, %f429, %f439;
	sub.f32 	%f885, %f438, %f440;
	bra.uni 	BB1_127;

BB1_115:
	mov.b32 	 %r83, %f628;
	and.b32  	%r620, %r83, -2147483648;
	shr.u32 	%r85, %r83, 23;
	and.b32  	%r410, %r85, 255;
	add.s32 	%r411, %r410, -128;
	shl.b32 	%r412, %r83, 8;
	or.b32  	%r409, %r412, -2147483648;
	shr.u32 	%r413, %r411, 5;
	mov.u32 	%r414, 4;
	sub.s32 	%r415, %r414, %r413;
	ld.const.u32 	%r393, [__GPU_i2opi_f];
	mul.lo.s32 	%r416, %r393, %r409;
	// inline asm
	mul.hi.u32 	%r392, %r393, %r409;
	// inline asm
	st.local.u32 	[%r5], %r416;
	ld.const.u32 	%r396, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r417, %r396, %r409;
	// inline asm
	mul.hi.u32 	%r395, %r396, %r409;
	// inline asm
	mad.lo.s32 	%r418, %r396, %r409, %r392;
	setp.lt.u32 	%p81, %r418, %r417;
	selp.u32 	%r419, 1, 0, %p81;
	add.s32 	%r420, %r419, %r395;
	st.local.u32 	[%r5+4], %r418;
	ld.const.u32 	%r399, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r421, %r399, %r409;
	// inline asm
	mul.hi.u32 	%r398, %r399, %r409;
	// inline asm
	mad.lo.s32 	%r422, %r399, %r409, %r420;
	setp.lt.u32 	%p82, %r422, %r421;
	selp.u32 	%r423, 1, 0, %p82;
	add.s32 	%r424, %r423, %r398;
	st.local.u32 	[%r5+8], %r422;
	ld.const.u32 	%r402, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r425, %r402, %r409;
	// inline asm
	mul.hi.u32 	%r401, %r402, %r409;
	// inline asm
	mad.lo.s32 	%r426, %r402, %r409, %r424;
	setp.lt.u32 	%p83, %r426, %r425;
	selp.u32 	%r427, 1, 0, %p83;
	add.s32 	%r428, %r427, %r401;
	st.local.u32 	[%r5+12], %r426;
	ld.const.u32 	%r405, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r429, %r405, %r409;
	// inline asm
	mul.hi.u32 	%r404, %r405, %r409;
	// inline asm
	mad.lo.s32 	%r430, %r405, %r409, %r428;
	setp.lt.u32 	%p84, %r430, %r429;
	selp.u32 	%r431, 1, 0, %p84;
	add.s32 	%r432, %r431, %r404;
	st.local.u32 	[%r5+16], %r430;
	ld.const.u32 	%r408, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r433, %r408, %r409;
	// inline asm
	mul.hi.u32 	%r407, %r408, %r409;
	// inline asm
	mad.lo.s32 	%r434, %r408, %r409, %r432;
	setp.lt.u32 	%p85, %r434, %r433;
	selp.u32 	%r435, 1, 0, %p85;
	add.s32 	%r436, %r435, %r407;
	st.local.u32 	[%r5+20], %r434;
	st.local.u32 	[%r5+24], %r436;
	and.b32  	%r86, %r85, 31;
	shl.b32 	%r438, %r415, 2;
	add.s32 	%r439, %r438, %r5;
	add.s32 	%r87, %r439, -16;
	ld.local.u32 	%r618, [%r439+8];
	ld.local.u32 	%r619, [%r439+4];
	setp.eq.s32 	%p86, %r86, 0;
	@%p86 bra 	BB1_117;

	shl.b32 	%r440, %r618, %r86;
	neg.s32 	%r441, %r85;
	and.b32  	%r442, %r441, 31;
	shr.u32 	%r443, %r619, %r442;
	or.b32  	%r618, %r443, %r440;
	ld.local.u32 	%r444, [%r87+16];
	shr.u32 	%r445, %r444, %r442;
	shl.b32 	%r446, %r619, %r86;
	or.b32  	%r619, %r445, %r446;

BB1_117:
	shr.u32 	%r447, %r619, 30;
	shl.b32 	%r448, %r618, 2;
	or.b32  	%r624, %r447, %r448;
	shl.b32 	%r95, %r619, 2;
	setp.ne.s32 	%p87, %r95, 0;
	selp.u32 	%r449, 1, 0, %p87;
	add.s32 	%r450, %r449, %r624;
	setp.gt.u32 	%p88, %r450, -2147483648;
	selp.u32 	%r451, 1, 0, %p88;
	shr.u32 	%r452, %r618, 30;
	add.s32 	%r453, %r451, %r452;
	neg.s32 	%r454, %r453;
	setp.lt.s32 	%p89, %r83, 0;
	selp.b32 	%r628, %r454, %r453, %p89;
	@%p88 bra 	BB1_119;

	mov.u32 	%r623, %r95;
	bra.uni 	BB1_120;

BB1_119:
	not.b32 	%r455, %r624;
	neg.s32 	%r97, %r95;
	setp.eq.s32 	%p90, %r95, 0;
	selp.u32 	%r456, 1, 0, %p90;
	add.s32 	%r624, %r456, %r455;
	xor.b32  	%r620, %r620, -2147483648;
	mov.u32 	%r623, %r97;

BB1_120:
	mov.u32 	%r622, %r623;
	setp.gt.s32 	%p91, %r624, 0;
	@%p91 bra 	BB1_122;

	mov.u32 	%r627, 0;
	bra.uni 	BB1_124;

BB1_122:
	mov.u32 	%r627, 0;

BB1_123:
	shr.u32 	%r459, %r622, 31;
	shl.b32 	%r460, %r624, 1;
	or.b32  	%r624, %r459, %r460;
	shl.b32 	%r622, %r622, 1;
	add.s32 	%r627, %r627, -1;
	setp.gt.s32 	%p92, %r624, 0;
	@%p92 bra 	BB1_123;

BB1_124:
	mul.lo.s32 	%r626, %r624, -921707870;
	mov.u32 	%r463, -921707870;
	// inline asm
	mul.hi.u32 	%r461, %r624, %r463;
	// inline asm
	setp.gt.s32 	%p93, %r461, 0;
	mov.u32 	%r625, %r461;
	@%p93 bra 	BB1_125;
	bra.uni 	BB1_126;

BB1_125:
	shl.b32 	%r464, %r461, 1;
	shr.u32 	%r465, %r626, 31;
	or.b32  	%r625, %r464, %r465;
	mul.lo.s32 	%r626, %r624, -1843415740;
	add.s32 	%r627, %r627, -1;

BB1_126:
	setp.ne.s32 	%p94, %r626, 0;
	selp.u32 	%r466, 1, 0, %p94;
	add.s32 	%r467, %r466, %r625;
	shr.u32 	%r468, %r467, 8;
	shr.u32 	%r469, %r467, 7;
	and.b32  	%r470, %r469, 1;
	shl.b32 	%r471, %r627, 23;
	add.s32 	%r472, %r471, %r468;
	add.s32 	%r473, %r472, %r470;
	add.s32 	%r474, %r473, 1056964608;
	or.b32  	%r475, %r474, %r620;
	mov.b32 	 %f885, %r475;

BB1_127:
	and.b32  	%r476, %r628, 1;
	setp.eq.s32 	%p95, %r476, 0;
	mul.rn.f32 	%f87, %f885, %f885;
	@%p95 bra 	BB1_129;

	mov.f32 	%f441, 0f37CCF5CE;
	mul.rn.f32 	%f442, %f441, %f87;
	add.f32 	%f443, %f442, 0fBAB6061A;
	mul.rn.f32 	%f444, %f443, %f87;
	add.f32 	%f445, %f444, 0f3D2AAAA5;
	mul.rn.f32 	%f446, %f445, %f87;
	add.f32 	%f447, %f446, 0fBF000000;
	mul.rn.f32 	%f448, %f447, %f87;
	add.f32 	%f886, %f448, 0f3F800000;
	bra.uni 	BB1_130;

BB1_129:
	mov.f32 	%f449, 0fB94CA1F9;
	mul.rn.f32 	%f450, %f449, %f87;
	add.f32 	%f451, %f450, 0f3C08839E;
	mul.rn.f32 	%f452, %f451, %f87;
	add.f32 	%f453, %f452, 0fBE2AAAA3;
	mul.rn.f32 	%f454, %f453, %f87;
	mul.rn.f32 	%f455, %f454, %f885;
	add.f32 	%f886, %f455, %f885;

BB1_130:
	and.b32  	%r477, %r628, 2;
	setp.eq.s32 	%p96, %r477, 0;
	neg.f32 	%f456, %f886;
	selp.f32 	%f887, %f886, %f456, %p96;
	bra.uni 	BB1_132;

BB1_131:
	mov.f32 	%f457, 0f00000000;
	mul.rn.f32 	%f887, %f628, %f457;

BB1_132:
	setp.eq.f32 	%p97, %f629, %f61;
	@%p97 bra 	BB1_152;

	setp.eq.f32 	%p98, %f629, 0fFF800000;
	setp.eq.f32 	%p99, %f629, 0f00000000;
	or.pred  	%p100, %p98, %p99;
	@%p100 bra 	BB1_152;

	// inline asm
	abs.f32 	%f458, %f629;
	// inline asm
	setp.gt.f32 	%p101, %f458, 0f473BA700;
	@%p101 bra 	BB1_136;

	mov.f32 	%f462, 0f3F22F983;
	mul.rn.f32 	%f461, %f629, %f462;
	// inline asm
	cvt.rni.f32.f32 	%f460, %f461;
	// inline asm
	cvt.rzi.s32.f32 	%r639, %f460;
	cvt.rn.f32.s32 	%f463, %r639;
	mov.f32 	%f464, 0f3FC90000;
	mul.rn.f32 	%f465, %f463, %f464;
	sub.f32 	%f466, %f629, %f465;
	mov.f32 	%f467, 0f39FD8000;
	mul.rn.f32 	%f468, %f463, %f467;
	sub.f32 	%f469, %f466, %f468;
	mov.f32 	%f470, 0f34A88000;
	mul.rn.f32 	%f471, %f463, %f470;
	sub.f32 	%f472, %f469, %f471;
	mov.f32 	%f473, 0f2E85A309;
	mul.rn.f32 	%f474, %f463, %f473;
	sub.f32 	%f888, %f472, %f474;
	bra.uni 	BB1_148;

BB1_136:
	mov.b32 	 %r121, %f629;
	and.b32  	%r631, %r121, -2147483648;
	shr.u32 	%r123, %r121, 23;
	and.b32  	%r496, %r123, 255;
	add.s32 	%r497, %r496, -128;
	shl.b32 	%r498, %r121, 8;
	or.b32  	%r495, %r498, -2147483648;
	shr.u32 	%r499, %r497, 5;
	mov.u32 	%r500, 4;
	sub.s32 	%r501, %r500, %r499;
	ld.const.u32 	%r479, [__GPU_i2opi_f];
	mul.lo.s32 	%r502, %r479, %r495;
	// inline asm
	mul.hi.u32 	%r478, %r479, %r495;
	// inline asm
	st.local.u32 	[%r5], %r502;
	ld.const.u32 	%r482, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r503, %r482, %r495;
	// inline asm
	mul.hi.u32 	%r481, %r482, %r495;
	// inline asm
	mad.lo.s32 	%r504, %r482, %r495, %r478;
	setp.lt.u32 	%p102, %r504, %r503;
	selp.u32 	%r505, 1, 0, %p102;
	add.s32 	%r506, %r505, %r481;
	st.local.u32 	[%r5+4], %r504;
	ld.const.u32 	%r485, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r507, %r485, %r495;
	// inline asm
	mul.hi.u32 	%r484, %r485, %r495;
	// inline asm
	mad.lo.s32 	%r508, %r485, %r495, %r506;
	setp.lt.u32 	%p103, %r508, %r507;
	selp.u32 	%r509, 1, 0, %p103;
	add.s32 	%r510, %r509, %r484;
	st.local.u32 	[%r5+8], %r508;
	ld.const.u32 	%r488, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r511, %r488, %r495;
	// inline asm
	mul.hi.u32 	%r487, %r488, %r495;
	// inline asm
	mad.lo.s32 	%r512, %r488, %r495, %r510;
	setp.lt.u32 	%p104, %r512, %r511;
	selp.u32 	%r513, 1, 0, %p104;
	add.s32 	%r514, %r513, %r487;
	st.local.u32 	[%r5+12], %r512;
	ld.const.u32 	%r491, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r515, %r491, %r495;
	// inline asm
	mul.hi.u32 	%r490, %r491, %r495;
	// inline asm
	mad.lo.s32 	%r516, %r491, %r495, %r514;
	setp.lt.u32 	%p105, %r516, %r515;
	selp.u32 	%r517, 1, 0, %p105;
	add.s32 	%r518, %r517, %r490;
	st.local.u32 	[%r5+16], %r516;
	ld.const.u32 	%r494, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r519, %r494, %r495;
	// inline asm
	mul.hi.u32 	%r493, %r494, %r495;
	// inline asm
	mad.lo.s32 	%r520, %r494, %r495, %r518;
	setp.lt.u32 	%p106, %r520, %r519;
	selp.u32 	%r521, 1, 0, %p106;
	add.s32 	%r522, %r521, %r493;
	st.local.u32 	[%r5+20], %r520;
	st.local.u32 	[%r5+24], %r522;
	and.b32  	%r124, %r123, 31;
	shl.b32 	%r524, %r501, 2;
	add.s32 	%r525, %r524, %r5;
	add.s32 	%r125, %r525, -16;
	ld.local.u32 	%r629, [%r525+8];
	ld.local.u32 	%r630, [%r525+4];
	setp.eq.s32 	%p107, %r124, 0;
	@%p107 bra 	BB1_138;

	shl.b32 	%r526, %r629, %r124;
	neg.s32 	%r527, %r123;
	and.b32  	%r528, %r527, 31;
	shr.u32 	%r529, %r630, %r528;
	or.b32  	%r629, %r529, %r526;
	ld.local.u32 	%r530, [%r125+16];
	shr.u32 	%r531, %r530, %r528;
	shl.b32 	%r532, %r630, %r124;
	or.b32  	%r630, %r531, %r532;

BB1_138:
	shr.u32 	%r533, %r630, 30;
	shl.b32 	%r534, %r629, 2;
	or.b32  	%r635, %r533, %r534;
	shl.b32 	%r133, %r630, 2;
	setp.ne.s32 	%p108, %r133, 0;
	selp.u32 	%r535, 1, 0, %p108;
	add.s32 	%r536, %r535, %r635;
	setp.gt.u32 	%p109, %r536, -2147483648;
	selp.u32 	%r537, 1, 0, %p109;
	shr.u32 	%r538, %r629, 30;
	add.s32 	%r539, %r537, %r538;
	neg.s32 	%r540, %r539;
	setp.lt.s32 	%p110, %r121, 0;
	selp.b32 	%r639, %r540, %r539, %p110;
	@%p109 bra 	BB1_140;

	mov.u32 	%r634, %r133;
	bra.uni 	BB1_141;

BB1_140:
	not.b32 	%r541, %r635;
	neg.s32 	%r135, %r133;
	setp.eq.s32 	%p111, %r133, 0;
	selp.u32 	%r542, 1, 0, %p111;
	add.s32 	%r635, %r542, %r541;
	xor.b32  	%r631, %r631, -2147483648;
	mov.u32 	%r634, %r135;

BB1_141:
	mov.u32 	%r633, %r634;
	setp.gt.s32 	%p112, %r635, 0;
	@%p112 bra 	BB1_143;

	mov.u32 	%r638, 0;
	bra.uni 	BB1_145;

BB1_143:
	mov.u32 	%r638, 0;

BB1_144:
	shr.u32 	%r545, %r633, 31;
	shl.b32 	%r546, %r635, 1;
	or.b32  	%r635, %r545, %r546;
	shl.b32 	%r633, %r633, 1;
	add.s32 	%r638, %r638, -1;
	setp.gt.s32 	%p113, %r635, 0;
	@%p113 bra 	BB1_144;

BB1_145:
	mul.lo.s32 	%r637, %r635, -921707870;
	mov.u32 	%r549, -921707870;
	// inline asm
	mul.hi.u32 	%r547, %r635, %r549;
	// inline asm
	setp.gt.s32 	%p114, %r547, 0;
	mov.u32 	%r636, %r547;
	@%p114 bra 	BB1_146;
	bra.uni 	BB1_147;

BB1_146:
	shl.b32 	%r550, %r547, 1;
	shr.u32 	%r551, %r637, 31;
	or.b32  	%r636, %r550, %r551;
	mul.lo.s32 	%r637, %r635, -1843415740;
	add.s32 	%r638, %r638, -1;

BB1_147:
	setp.ne.s32 	%p115, %r637, 0;
	selp.u32 	%r552, 1, 0, %p115;
	add.s32 	%r553, %r552, %r636;
	shr.u32 	%r554, %r553, 8;
	shr.u32 	%r555, %r553, 7;
	and.b32  	%r556, %r555, 1;
	shl.b32 	%r557, %r638, 23;
	add.s32 	%r558, %r557, %r554;
	add.s32 	%r559, %r558, %r556;
	add.s32 	%r560, %r559, 1056964608;
	or.b32  	%r561, %r560, %r631;
	mov.b32 	 %f888, %r561;

BB1_148:
	and.b32  	%r562, %r639, 1;
	setp.eq.s32 	%p116, %r562, 0;
	mul.rn.f32 	%f98, %f888, %f888;
	@%p116 bra 	BB1_150;

	mov.f32 	%f475, 0f37CCF5CE;
	mul.rn.f32 	%f476, %f475, %f98;
	add.f32 	%f477, %f476, 0fBAB6061A;
	mul.rn.f32 	%f478, %f477, %f98;
	add.f32 	%f479, %f478, 0f3D2AAAA5;
	mul.rn.f32 	%f480, %f479, %f98;
	add.f32 	%f481, %f480, 0fBF000000;
	mul.rn.f32 	%f482, %f481, %f98;
	add.f32 	%f889, %f482, 0f3F800000;
	bra.uni 	BB1_151;

BB1_150:
	mov.f32 	%f483, 0fB94CA1F9;
	mul.rn.f32 	%f484, %f483, %f98;
	add.f32 	%f485, %f484, 0f3C08839E;
	mul.rn.f32 	%f486, %f485, %f98;
	add.f32 	%f487, %f486, 0fBE2AAAA3;
	mul.rn.f32 	%f488, %f487, %f98;
	mul.rn.f32 	%f489, %f488, %f888;
	add.f32 	%f889, %f489, %f888;

BB1_151:
	and.b32  	%r563, %r639, 2;
	setp.eq.s32 	%p117, %r563, 0;
	neg.f32 	%f490, %f889;
	selp.f32 	%f890, %f889, %f490, %p117;
	bra.uni 	BB1_153;

BB1_152:
	mov.f32 	%f491, 0f00000000;
	mul.rn.f32 	%f890, %f629, %f491;

BB1_153:
	mad.f32 	%f610, %f877, %f881, %f878;
	mad.f32 	%f611, %f877, %f884, %f878;
	mad.f32 	%f612, %f877, %f887, %f878;
	mad.f32 	%f613, %f877, %f890, %f878;
	mov.f32 	%f495, 0f477FFF00;
	mul.f32 	%f891, %f610, %f495;
	mul.f32 	%f892, %f611, %f495;
	mul.f32 	%f893, %f612, %f495;
	mul.f32 	%f894, %f613, %f495;
	bra.uni 	BB1_159;

BB1_154:
	ld.param.u32 	%r570, [FunctionImage_param_3];
	setp.eq.s32 	%p118, %r570, 0;
	@%p118 bra 	BB1_158;

	mov.f32 	%f496, 0f00000000;
	mov.f32 	%f895, %f496;
	mov.f32 	%f896, %f496;
	mov.f32 	%f897, %f496;
	mov.f32 	%f898, %f496;
	mov.u32 	%r641, 0;
	ld.param.u32 	%r640, [FunctionImage_param_4];

BB1_156:
	mov.f32 	%f497, 0f377BA882;
	mul.f32 	%f570, %f895, %f497;
	mul.f32 	%f571, %f896, %f497;
	mul.f32 	%f572, %f897, %f497;
	mul.f32 	%f573, %f898, %f497;
	ld.const.f32 	%f498, [%r640];
	mad.f32 	%f895, %f570, %f586, %f498;
	mad.f32 	%f896, %f571, %f587, %f498;
	mad.f32 	%f897, %f572, %f588, %f498;
	mad.f32 	%f898, %f573, %f589, %f498;
	add.s32 	%r640, %r640, 4;
	add.s32 	%r641, %r641, 1;
	ld.param.u32 	%r569, [FunctionImage_param_3];
	setp.lt.u32 	%p119, %r641, %r569;
	@%p119 bra 	BB1_156;

	mov.f32 	%f502, 0f477FFF00;
	mul.f32 	%f891, %f895, %f502;
	mul.f32 	%f892, %f896, %f502;
	mul.f32 	%f893, %f897, %f502;
	mul.f32 	%f894, %f898, %f502;
	bra.uni 	BB1_159;

BB1_158:
	mov.f32 	%f503, 0f00000000;
	mov.f32 	%f891, %f503;
	mov.f32 	%f892, %f503;
	mov.f32 	%f893, %f503;
	mov.f32 	%f894, %f503;

BB1_159:
	mov.f32 	%f505, 0f00000000;
	max.f32 	%f506, %f891, %f505;
	mov.f32 	%f507, 0f477FFF00;
	min.f32 	%f508, %f506, %f507;
	add.f32 	%f509, %f508, 0f3F000000;
	max.f32 	%f511, %f892, %f505;
	min.f32 	%f512, %f511, %f507;
	add.f32 	%f513, %f512, 0f3F000000;
	max.f32 	%f515, %f893, %f505;
	min.f32 	%f516, %f515, %f507;
	add.f32 	%f517, %f516, 0f3F000000;
	max.f32 	%f519, %f894, %f505;
	min.f32 	%f520, %f519, %f507;
	add.f32 	%f521, %f520, 0f3F000000;
	st.global.v4.f32 	[%r4], {%f509, %f513, %f517, %f521};
	ret;
}

.entry Equalize(
	.param .u32 .ptr .global .align 16 Equalize_param_0,
	.param .u32 Equalize_param_1,
	.param .u32 .ptr .global .align 16 Equalize_param_2,
	.param .align 16 .b8 Equalize_param_3[16],
	.param .align 16 .b8 Equalize_param_4[16]
)
{
	.reg .f32 	%f<47>;
	.reg .pred 	%p<7>;
	.reg .s32 	%r<49>;
	.reg .s16 	%rc<3>;


	ld.param.u32 	%r21, [Equalize_param_0];
	ld.param.v4.f32 	{%f43, %f44, %f45, %f46}, [Equalize_param_4];
	ld.param.v4.f32 	{%f39, %f40, %f41, %f42}, [Equalize_param_3];
	// inline asm
	mov.u32 	%r11, %envreg3;
	// inline asm
	// inline asm
	mov.u32 	%r12, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r13, %ctaid.x;
	// inline asm
	// inline asm
	mov.u32 	%r14, %tid.x;
	// inline asm
	// inline asm
	mov.u32 	%r15, %envreg4;
	// inline asm
	// inline asm
	mov.u32 	%r16, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r17, %ctaid.y;
	// inline asm
	// inline asm
	mov.u32 	%r18, %tid.y;
	// inline asm
	add.s32 	%r22, %r18, %r15;
	mad.lo.s32 	%r23, %r17, %r16, %r22;
	// inline asm
	mov.u32 	%r19, %envreg6;
	// inline asm
	// inline asm
	mov.u32 	%r20, %ntid.x;
	// inline asm
	mul.lo.s32 	%r24, %r23, %r19;
	mad.lo.s32 	%r25, %r13, %r12, %r11;
	add.s32 	%r26, %r25, %r14;
	mad.lo.s32 	%r27, %r24, %r20, %r26;
	shl.b32 	%r28, %r27, 4;
	add.s32 	%r2, %r21, %r28;
	ld.global.v4.f32 	{%f35, %f36, %f37, %f38}, [%r2];
	ld.param.u8 	%rc1, [Equalize_param_1+1];
	and.b16  	%rc2, %rc1, 1;
	{
	.reg .s16 	%temp1;
	.reg .s16 	%temp2;
	cvt.s16.s8 	%temp1, %rc2;
	mov.b16 	%temp2, 0;
	cvt.s16.s8 	%temp2, %temp2;
	setp.eq.s16 	%p1, %temp1, %temp2;
	}
	@%p1 bra 	BB2_15;

	setp.eq.f32 	%p2, %f41, %f45;
	@%p2 bra 	BB2_15;

	setp.ltu.f32 	%p3, %f37, 0f477FFF00;
	@%p3 bra 	BB2_4;

	mov.u32 	%r45, 65535;
	bra.uni 	BB2_5;

BB2_4:
	cvt.rzi.u32.f32 	%r45, %f37;

BB2_5:
	shl.b32 	%r30, %r45, 4;
	ld.param.u32 	%r44, [Equalize_param_2];
	add.s32 	%r31, %r44, %r30;
	ld.global.v4.f32 	{%f23, %f24, %f25, %f26}, [%r31];
	setp.ltu.f32 	%p4, %f36, 0f477FFF00;
	@%p4 bra 	BB2_7;

	mov.u32 	%r46, 65535;
	bra.uni 	BB2_8;

BB2_7:
	cvt.rzi.u32.f32 	%r46, %f36;

BB2_8:
	shl.b32 	%r33, %r46, 4;
	ld.param.u32 	%r43, [Equalize_param_2];
	add.s32 	%r34, %r43, %r33;
	ld.global.v4.f32 	{%f15, %f16, %f17, %f18}, [%r34];
	setp.ltu.f32 	%p5, %f35, 0f477FFF00;
	@%p5 bra 	BB2_10;

	mov.u32 	%r47, 65535;
	bra.uni 	BB2_11;

BB2_10:
	cvt.rzi.u32.f32 	%r47, %f35;

BB2_11:
	shl.b32 	%r36, %r47, 4;
	ld.param.u32 	%r42, [Equalize_param_2];
	add.s32 	%r37, %r42, %r36;
	ld.global.v4.f32 	{%f11, %f12, %f13, %f14}, [%r37];
	setp.ltu.f32 	%p6, %f38, 0f477FFF00;
	@%p6 bra 	BB2_13;

	mov.u32 	%r48, 65535;
	bra.uni 	BB2_14;

BB2_13:
	cvt.rzi.u32.f32 	%r48, %f38;

BB2_14:
	shl.b32 	%r39, %r48, 4;
	ld.param.u32 	%r41, [Equalize_param_2];
	add.s32 	%r40, %r41, %r39;
	ld.global.v4.f32 	{%f27, %f28, %f29, %f30}, [%r40];
	st.global.v4.f32 	[%r2], {%f13, %f17, %f25, %f29};

BB2_15:
	ret;
}

.entry Histogram(
	.param .u32 .ptr .global .align 16 Histogram_param_0,
	.param .u32 Histogram_param_1,
	.param .u32 Histogram_param_2,
	.param .u32 .ptr .global .align 16 Histogram_param_3
)
{
	.reg .f32 	%f<17>;
	.reg .pred 	%p<4>;
	.reg .s32 	%r<33>;
	.reg .s16 	%rc<3>;


	// inline asm
	mov.u32 	%r7, %envreg3;
	// inline asm
	// inline asm
	mov.u32 	%r8, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r9, %ctaid.x;
	// inline asm
	// inline asm
	mov.u32 	%r10, %tid.x;
	// inline asm
	// inline asm
	mov.u32 	%r11, %envreg4;
	// inline asm
	// inline asm
	mov.u32 	%r12, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r13, %ctaid.y;
	// inline asm
	// inline asm
	mov.u32 	%r14, %tid.y;
	// inline asm
	add.s32 	%r17, %r14, %r11;
	mad.lo.s32 	%r18, %r13, %r12, %r17;
	// inline asm
	mov.u32 	%r15, %envreg6;
	// inline asm
	// inline asm
	mov.u32 	%r16, %ntid.x;
	// inline asm
	mul.lo.s32 	%r19, %r18, %r15;
	add.s32 	%r20, %r10, %r7;
	mad.lo.s32 	%r21, %r9, %r8, %r20;
	mad.lo.s32 	%r4, %r19, %r16, %r21;
	ld.param.u8 	%rc1, [Histogram_param_1+1];
	and.b16  	%rc2, %rc1, 1;
	{
	.reg .s16 	%temp1;
	.reg .s16 	%temp2;
	cvt.s16.s8 	%temp1, %rc2;
	mov.b16 	%temp2, 0;
	cvt.s16.s8 	%temp2, %temp2;
	setp.eq.s16 	%p1, %temp1, %temp2;
	}
	@%p1 bra 	BB3_5;

	shl.b32 	%r22, %r4, 4;
	ld.param.u32 	%r29, [Histogram_param_0];
	add.s32 	%r23, %r29, %r22;
	ld.global.v4.f32 	{%f13, %f14, %f15, %f16}, [%r23];
	mul.f32 	%f5, %f14, 0f3F371498;
	mad.f32 	%f6, %f15, 0f3E59C27F, %f5;
	mad.f32 	%f7, %f13, 0f3D93D641, %f6;
	ld.param.u32 	%r30, [Histogram_param_2];
	setp.eq.s32 	%p2, %r30, 0;
	selp.f32 	%f8, %f7, 0f00000000, %p2;
	mov.f32 	%f9, 0f00000000;
	max.f32 	%f10, %f8, %f9;
	mov.f32 	%f11, 0f477FFF00;
	min.f32 	%f12, %f10, %f11;
	add.f32 	%f1, %f12, 0f3F000000;
	setp.ltu.f32 	%p3, %f1, 0f477FFF00;
	@%p3 bra 	BB3_3;

	mov.u32 	%r32, 65535;
	bra.uni 	BB3_4;

BB3_3:
	cvt.rzi.u32.f32 	%r32, %f1;

BB3_4:
	shl.b32 	%r25, %r32, 4;
	ld.param.u32 	%r31, [Histogram_param_3];
	add.s32 	%r26, %r31, %r25;
	add.s32 	%r27, %r26, 8;
	atom.global.add.u32 	%r28, [%r27], 1;

BB3_5:
	ret;
}

.entry BlurRow(
	.param .u32 .ptr .global .align 16 BlurRow_param_0,
	.param .u32 .ptr .global .align 16 BlurRow_param_1,
	.param .u32 BlurRow_param_2,
	.param .u32 .ptr .const .align 4 BlurRow_param_3,
	.param .u32 BlurRow_param_4,
	.param .u32 BlurRow_param_5,
	.param .u32 BlurRow_param_6,
	.param .u32 .ptr .shared .align 16 BlurRow_param_7
)
{
	.reg .f32 	%f<273>;
	.reg .pred 	%p<8>;
	.reg .s32 	%r<133>;


	ld.param.u32 	%r4, [BlurRow_param_4];
	// inline asm
	mov.u32 	%r28, %envreg3;
	// inline asm
	// inline asm
	mov.u32 	%r29, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r30, %ctaid.x;
	// inline asm
	mul.lo.s32 	%r8, %r30, %r29;
	// inline asm
	mov.u32 	%r31, %tid.x;
	// inline asm
	// inline asm
	mov.u32 	%r32, %envreg4;
	// inline asm
	// inline asm
	mov.u32 	%r33, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r34, %ctaid.y;
	// inline asm
	// inline asm
	mov.u32 	%r35, %tid.y;
	// inline asm
	add.s32 	%r44, %r35, %r32;
	mad.lo.s32 	%r10, %r34, %r33, %r44;
	add.s32 	%r45, %r4, -1;
	shr.u32 	%r11, %r45, 1;
	// inline asm
	mov.u32 	%r36, %ntid.x;
	// inline asm
	add.s32 	%r12, %r36, %r4;
	// inline asm
	mov.u32 	%r37, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r38, %envreg0;
	// inline asm
	// inline asm
	mov.u32 	%r39, %ctaid.x;
	// inline asm
	add.s32 	%r46, %r39, %r38;
	mul.lo.s32 	%r13, %r46, %r37;
	// inline asm
	mov.u32 	%r43, %tid.x;
	// inline asm
	setp.ge.u32 	%p1, %r43, %r12;
	mov.u32 	%r126, %r43;
	@%p1 bra 	BB4_3;

	ld.param.u32 	%r122, [BlurRow_param_5];
	mul.lo.s32 	%r15, %r10, %r122;
	sub.s32 	%r16, %r13, %r11;
	add.s32 	%r17, %r122, -1;

BB4_2:
	add.s32 	%r48, %r16, %r126;
	mov.u32 	%r49, 0;
	// inline asm
	max.s32 	%r47, %r48, %r49;
	// inline asm
	// inline asm
	min.s32 	%r50, %r47, %r17;
	// inline asm
	add.s32 	%r54, %r50, %r15;
	shl.b32 	%r55, %r54, 4;
	ld.param.u32 	%r112, [BlurRow_param_0];
	add.s32 	%r56, %r112, %r55;
	shl.b32 	%r57, %r126, 4;
	ld.param.u32 	%r125, [BlurRow_param_7];
	add.s32 	%r58, %r125, %r57;
	ld.global.v4.f32 	{%f265, %f266, %f267, %f268}, [%r56];
	st.shared.v4.f32 	[%r58], {%f265, %f266, %f267, %f268};
	// inline asm
	mov.u32 	%r53, %ntid.x;
	// inline asm
	add.s32 	%r126, %r53, %r126;
	setp.lt.u32 	%p2, %r126, %r12;
	@%p2 bra 	BB4_2;

BB4_3:
	bar.sync 	0;
	// inline asm
	mov.u32 	%r59, %envreg3;
	// inline asm
	// inline asm
	mov.u32 	%r60, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r61, %ctaid.x;
	// inline asm
	// inline asm
	mov.u32 	%r62, %tid.x;
	// inline asm
	add.s32 	%r63, %r62, %r59;
	mad.lo.s32 	%r64, %r61, %r60, %r63;
	ld.param.u32 	%r121, [BlurRow_param_5];
	setp.lt.u32 	%p3, %r64, %r121;
	@%p3 bra 	BB4_5;

	ret;

BB4_5:
	ld.param.u32 	%r119, [BlurRow_param_4];
	setp.gt.u32 	%p4, %r119, 8;
	@%p4 bra 	BB4_7;

	mov.f32 	%f1, 0f00000000;
	mov.f32 	%f269, %f1;
	mov.f32 	%f270, %f1;
	mov.f32 	%f271, %f1;
	mov.f32 	%f272, %f1;
	mov.u32 	%r131, 0;
	bra.uni 	BB4_10;

BB4_7:
	mov.f32 	%f2, 0f00000000;
	mov.f32 	%f269, %f2;
	mov.f32 	%f270, %f2;
	mov.f32 	%f271, %f2;
	mov.f32 	%f272, %f2;
	mov.u32 	%r132, 0;

BB4_8:
	mov.u32 	%r20, %r132;
	shl.b32 	%r75, %r20, 2;
	ld.param.u32 	%r115, [BlurRow_param_3];
	add.s32 	%r76, %r115, %r75;
	ld.const.f32 	%f3, [%r76];
	// inline asm
	mov.u32 	%r67, %tid.x;
	// inline asm
	add.s32 	%r77, %r67, %r20;
	shl.b32 	%r78, %r77, 4;
	ld.param.u32 	%r124, [BlurRow_param_7];
	add.s32 	%r79, %r124, %r78;
	ld.shared.v4.f32 	{%f121, %f122, %f123, %f124}, [%r79];
	mad.f32 	%f125, %f3, %f121, %f269;
	mad.f32 	%f126, %f3, %f122, %f270;
	mad.f32 	%f127, %f3, %f123, %f271;
	mad.f32 	%f128, %f3, %f124, %f272;
	ld.const.f32 	%f7, [%r76+4];
	// inline asm
	mov.u32 	%r68, %tid.x;
	// inline asm
	add.s32 	%r80, %r20, %r68;
	shl.b32 	%r81, %r80, 4;
	add.s32 	%r82, %r81, %r124;
	ld.shared.v4.f32 	{%f141, %f142, %f143, %f144}, [%r82+16];
	mad.f32 	%f145, %f7, %f141, %f125;
	mad.f32 	%f146, %f7, %f142, %f126;
	mad.f32 	%f147, %f7, %f143, %f127;
	mad.f32 	%f148, %f7, %f144, %f128;
	ld.const.f32 	%f11, [%r76+8];
	// inline asm
	mov.u32 	%r69, %tid.x;
	// inline asm
	add.s32 	%r83, %r20, %r69;
	shl.b32 	%r84, %r83, 4;
	add.s32 	%r85, %r84, %r124;
	ld.shared.v4.f32 	{%f161, %f162, %f163, %f164}, [%r85+32];
	mad.f32 	%f165, %f11, %f161, %f145;
	mad.f32 	%f166, %f11, %f162, %f146;
	mad.f32 	%f167, %f11, %f163, %f147;
	mad.f32 	%f168, %f11, %f164, %f148;
	ld.const.f32 	%f15, [%r76+12];
	// inline asm
	mov.u32 	%r70, %tid.x;
	// inline asm
	add.s32 	%r86, %r20, %r70;
	shl.b32 	%r87, %r86, 4;
	add.s32 	%r88, %r87, %r124;
	ld.shared.v4.f32 	{%f181, %f182, %f183, %f184}, [%r88+48];
	mad.f32 	%f185, %f15, %f181, %f165;
	mad.f32 	%f186, %f15, %f182, %f166;
	mad.f32 	%f187, %f15, %f183, %f167;
	mad.f32 	%f188, %f15, %f184, %f168;
	ld.const.f32 	%f19, [%r76+16];
	// inline asm
	mov.u32 	%r71, %tid.x;
	// inline asm
	add.s32 	%r89, %r20, %r71;
	shl.b32 	%r90, %r89, 4;
	add.s32 	%r91, %r90, %r124;
	ld.shared.v4.f32 	{%f201, %f202, %f203, %f204}, [%r91+64];
	mad.f32 	%f205, %f19, %f201, %f185;
	mad.f32 	%f206, %f19, %f202, %f186;
	mad.f32 	%f207, %f19, %f203, %f187;
	mad.f32 	%f208, %f19, %f204, %f188;
	ld.const.f32 	%f23, [%r76+20];
	// inline asm
	mov.u32 	%r72, %tid.x;
	// inline asm
	add.s32 	%r92, %r20, %r72;
	shl.b32 	%r93, %r92, 4;
	add.s32 	%r94, %r93, %r124;
	ld.shared.v4.f32 	{%f221, %f222, %f223, %f224}, [%r94+80];
	mad.f32 	%f225, %f23, %f221, %f205;
	mad.f32 	%f226, %f23, %f222, %f206;
	mad.f32 	%f227, %f23, %f223, %f207;
	mad.f32 	%f228, %f23, %f224, %f208;
	ld.const.f32 	%f27, [%r76+24];
	// inline asm
	mov.u32 	%r73, %tid.x;
	// inline asm
	add.s32 	%r95, %r20, %r73;
	shl.b32 	%r96, %r95, 4;
	add.s32 	%r97, %r96, %r124;
	ld.shared.v4.f32 	{%f241, %f242, %f243, %f244}, [%r97+96];
	mad.f32 	%f245, %f27, %f241, %f225;
	mad.f32 	%f246, %f27, %f242, %f226;
	mad.f32 	%f247, %f27, %f243, %f227;
	mad.f32 	%f248, %f27, %f244, %f228;
	ld.const.f32 	%f31, [%r76+28];
	// inline asm
	mov.u32 	%r74, %tid.x;
	// inline asm
	add.s32 	%r98, %r20, %r74;
	shl.b32 	%r99, %r98, 4;
	add.s32 	%r100, %r99, %r124;
	ld.shared.v4.f32 	{%f261, %f262, %f263, %f264}, [%r100+112];
	mad.f32 	%f269, %f31, %f261, %f245;
	mad.f32 	%f270, %f31, %f262, %f246;
	mad.f32 	%f271, %f31, %f263, %f247;
	mad.f32 	%f272, %f31, %f264, %f248;
	add.s32 	%r21, %r20, 8;
	add.s32 	%r101, %r20, 16;
	ld.param.u32 	%r118, [BlurRow_param_4];
	setp.lt.u32 	%p5, %r101, %r118;
	mov.u32 	%r132, %r21;
	@%p5 bra 	BB4_8;

	mov.u32 	%r131, %r21;

BB4_10:
	mov.u32 	%r130, %r131;
	ld.param.u32 	%r117, [BlurRow_param_4];
	setp.lt.u32 	%p6, %r130, %r117;
	@%p6 bra 	BB4_11;
	bra.uni 	BB4_13;

BB4_11:
	shl.b32 	%r102, %r130, 2;
	ld.param.u32 	%r114, [BlurRow_param_3];
	add.s32 	%r127, %r114, %r102;

BB4_12:
	ld.const.f32 	%f35, [%r127];
	// inline asm
	mov.u32 	%r103, %tid.x;
	// inline asm
	add.s32 	%r104, %r103, %r130;
	shl.b32 	%r105, %r104, 4;
	ld.param.u32 	%r123, [BlurRow_param_7];
	add.s32 	%r106, %r123, %r105;
	ld.shared.v4.f32 	{%f89, %f90, %f91, %f92}, [%r106];
	mad.f32 	%f269, %f35, %f89, %f269;
	mad.f32 	%f270, %f35, %f90, %f270;
	mad.f32 	%f271, %f35, %f91, %f271;
	mad.f32 	%f272, %f35, %f92, %f272;
	add.s32 	%r127, %r127, 4;
	add.s32 	%r130, %r130, 1;
	ld.param.u32 	%r116, [BlurRow_param_4];
	setp.lt.u32 	%p7, %r130, %r116;
	@%p7 bra 	BB4_12;

BB4_13:
	mov.f32 	%f40, 0f00000000;
	max.f32 	%f41, %f269, %f40;
	mov.f32 	%f42, 0f477FFF00;
	min.f32 	%f43, %f41, %f42;
	add.f32 	%f44, %f43, 0f3F000000;
	max.f32 	%f46, %f270, %f40;
	min.f32 	%f47, %f46, %f42;
	add.f32 	%f48, %f47, 0f3F000000;
	max.f32 	%f50, %f271, %f40;
	min.f32 	%f51, %f50, %f42;
	add.f32 	%f52, %f51, 0f3F000000;
	max.f32 	%f54, %f272, %f40;
	min.f32 	%f55, %f54, %f42;
	add.f32 	%f56, %f55, 0f3F000000;
	add.s32 	%r107, %r31, %r28;
	add.s32 	%r108, %r107, %r8;
	ld.param.u32 	%r120, [BlurRow_param_5];
	mad.lo.s32 	%r109, %r10, %r120, %r108;
	shl.b32 	%r110, %r109, 4;
	ld.param.u32 	%r113, [BlurRow_param_1];
	add.s32 	%r111, %r113, %r110;
	st.global.v4.f32 	[%r111], {%f44, %f48, %f52, %f56};
	ret;
}

.entry BlurColumn(
	.param .u32 .ptr .global .align 16 BlurColumn_param_0,
	.param .u32 .ptr .global .align 16 BlurColumn_param_1,
	.param .u32 BlurColumn_param_2,
	.param .u32 .ptr .const .align 4 BlurColumn_param_3,
	.param .u32 BlurColumn_param_4,
	.param .u32 BlurColumn_param_5,
	.param .u32 BlurColumn_param_6,
	.param .u32 .ptr .shared .align 16 BlurColumn_param_7
)
{
	.reg .f32 	%f<273>;
	.reg .pred 	%p<8>;
	.reg .s32 	%r<136>;


	ld.param.u32 	%r4, [BlurColumn_param_4];
	// inline asm
	mov.u32 	%r29, %envreg3;
	// inline asm
	// inline asm
	mov.u32 	%r30, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r31, %ctaid.x;
	// inline asm
	mul.lo.s32 	%r9, %r31, %r30;
	// inline asm
	mov.u32 	%r32, %tid.x;
	// inline asm
	// inline asm
	mov.u32 	%r33, %envreg4;
	// inline asm
	// inline asm
	mov.u32 	%r34, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r35, %ctaid.y;
	// inline asm
	// inline asm
	mov.u32 	%r36, %tid.y;
	// inline asm
	add.s32 	%r45, %r36, %r33;
	mad.lo.s32 	%r11, %r35, %r34, %r45;
	add.s32 	%r46, %r4, -1;
	shr.u32 	%r12, %r46, 1;
	// inline asm
	mov.u32 	%r37, %ntid.y;
	// inline asm
	add.s32 	%r13, %r37, %r4;
	// inline asm
	mov.u32 	%r38, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r39, %envreg0;
	// inline asm
	// inline asm
	mov.u32 	%r40, %ctaid.x;
	// inline asm
	add.s32 	%r47, %r40, %r39;
	mul.lo.s32 	%r14, %r47, %r38;
	// inline asm
	mov.u32 	%r41, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r42, %envreg1;
	// inline asm
	// inline asm
	mov.u32 	%r43, %ctaid.y;
	// inline asm
	add.s32 	%r48, %r43, %r42;
	mul.lo.s32 	%r15, %r48, %r41;
	// inline asm
	mov.u32 	%r44, %tid.y;
	// inline asm
	setp.ge.u32 	%p1, %r44, %r13;
	mov.u32 	%r129, %r44;
	@%p1 bra 	BB5_3;

	sub.s32 	%r17, %r15, %r12;
	ld.param.u32 	%r125, [BlurColumn_param_6];
	add.s32 	%r18, %r125, -1;

BB5_2:
	add.s32 	%r50, %r17, %r129;
	mov.u32 	%r51, 0;
	// inline asm
	max.s32 	%r49, %r50, %r51;
	// inline asm
	// inline asm
	min.s32 	%r52, %r49, %r18;
	// inline asm
	ld.param.u32 	%r123, [BlurColumn_param_5];
	mad.lo.s32 	%r56, %r52, %r123, %r14;
	shl.b32 	%r57, %r56, 4;
	ld.param.u32 	%r114, [BlurColumn_param_0];
	add.s32 	%r58, %r114, %r57;
	shl.b32 	%r59, %r129, 4;
	ld.param.u32 	%r128, [BlurColumn_param_7];
	add.s32 	%r60, %r128, %r59;
	ld.global.v4.f32 	{%f265, %f266, %f267, %f268}, [%r58];
	st.shared.v4.f32 	[%r60], {%f265, %f266, %f267, %f268};
	// inline asm
	mov.u32 	%r55, %ntid.y;
	// inline asm
	add.s32 	%r129, %r55, %r129;
	setp.lt.u32 	%p2, %r129, %r13;
	@%p2 bra 	BB5_2;

BB5_3:
	bar.sync 	0;
	// inline asm
	mov.u32 	%r61, %envreg4;
	// inline asm
	// inline asm
	mov.u32 	%r62, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r63, %ctaid.y;
	// inline asm
	// inline asm
	mov.u32 	%r64, %tid.y;
	// inline asm
	add.s32 	%r65, %r64, %r61;
	mad.lo.s32 	%r66, %r63, %r62, %r65;
	ld.param.u32 	%r124, [BlurColumn_param_6];
	setp.lt.u32 	%p3, %r66, %r124;
	@%p3 bra 	BB5_5;

	ret;

BB5_5:
	ld.param.u32 	%r121, [BlurColumn_param_4];
	setp.gt.u32 	%p4, %r121, 8;
	@%p4 bra 	BB5_7;

	mov.f32 	%f1, 0f00000000;
	mov.f32 	%f269, %f1;
	mov.f32 	%f270, %f1;
	mov.f32 	%f271, %f1;
	mov.f32 	%f272, %f1;
	mov.u32 	%r134, 0;
	bra.uni 	BB5_10;

BB5_7:
	mov.f32 	%f2, 0f00000000;
	mov.f32 	%f269, %f2;
	mov.f32 	%f270, %f2;
	mov.f32 	%f271, %f2;
	mov.f32 	%f272, %f2;
	mov.u32 	%r135, 0;

BB5_8:
	mov.u32 	%r21, %r135;
	shl.b32 	%r77, %r21, 2;
	ld.param.u32 	%r117, [BlurColumn_param_3];
	add.s32 	%r78, %r117, %r77;
	ld.const.f32 	%f3, [%r78];
	// inline asm
	mov.u32 	%r69, %tid.y;
	// inline asm
	add.s32 	%r79, %r69, %r21;
	shl.b32 	%r80, %r79, 4;
	ld.param.u32 	%r127, [BlurColumn_param_7];
	add.s32 	%r81, %r127, %r80;
	ld.shared.v4.f32 	{%f121, %f122, %f123, %f124}, [%r81];
	mad.f32 	%f125, %f3, %f121, %f269;
	mad.f32 	%f126, %f3, %f122, %f270;
	mad.f32 	%f127, %f3, %f123, %f271;
	mad.f32 	%f128, %f3, %f124, %f272;
	ld.const.f32 	%f7, [%r78+4];
	// inline asm
	mov.u32 	%r70, %tid.y;
	// inline asm
	add.s32 	%r82, %r21, %r70;
	shl.b32 	%r83, %r82, 4;
	add.s32 	%r84, %r83, %r127;
	ld.shared.v4.f32 	{%f141, %f142, %f143, %f144}, [%r84+16];
	mad.f32 	%f145, %f7, %f141, %f125;
	mad.f32 	%f146, %f7, %f142, %f126;
	mad.f32 	%f147, %f7, %f143, %f127;
	mad.f32 	%f148, %f7, %f144, %f128;
	ld.const.f32 	%f11, [%r78+8];
	// inline asm
	mov.u32 	%r71, %tid.y;
	// inline asm
	add.s32 	%r85, %r21, %r71;
	shl.b32 	%r86, %r85, 4;
	add.s32 	%r87, %r86, %r127;
	ld.shared.v4.f32 	{%f161, %f162, %f163, %f164}, [%r87+32];
	mad.f32 	%f165, %f11, %f161, %f145;
	mad.f32 	%f166, %f11, %f162, %f146;
	mad.f32 	%f167, %f11, %f163, %f147;
	mad.f32 	%f168, %f11, %f164, %f148;
	ld.const.f32 	%f15, [%r78+12];
	// inline asm
	mov.u32 	%r72, %tid.y;
	// inline asm
	add.s32 	%r88, %r21, %r72;
	shl.b32 	%r89, %r88, 4;
	add.s32 	%r90, %r89, %r127;
	ld.shared.v4.f32 	{%f181, %f182, %f183, %f184}, [%r90+48];
	mad.f32 	%f185, %f15, %f181, %f165;
	mad.f32 	%f186, %f15, %f182, %f166;
	mad.f32 	%f187, %f15, %f183, %f167;
	mad.f32 	%f188, %f15, %f184, %f168;
	ld.const.f32 	%f19, [%r78+16];
	// inline asm
	mov.u32 	%r73, %tid.y;
	// inline asm
	add.s32 	%r91, %r21, %r73;
	shl.b32 	%r92, %r91, 4;
	add.s32 	%r93, %r92, %r127;
	ld.shared.v4.f32 	{%f201, %f202, %f203, %f204}, [%r93+64];
	mad.f32 	%f205, %f19, %f201, %f185;
	mad.f32 	%f206, %f19, %f202, %f186;
	mad.f32 	%f207, %f19, %f203, %f187;
	mad.f32 	%f208, %f19, %f204, %f188;
	ld.const.f32 	%f23, [%r78+20];
	// inline asm
	mov.u32 	%r74, %tid.y;
	// inline asm
	add.s32 	%r94, %r21, %r74;
	shl.b32 	%r95, %r94, 4;
	add.s32 	%r96, %r95, %r127;
	ld.shared.v4.f32 	{%f221, %f222, %f223, %f224}, [%r96+80];
	mad.f32 	%f225, %f23, %f221, %f205;
	mad.f32 	%f226, %f23, %f222, %f206;
	mad.f32 	%f227, %f23, %f223, %f207;
	mad.f32 	%f228, %f23, %f224, %f208;
	ld.const.f32 	%f27, [%r78+24];
	// inline asm
	mov.u32 	%r75, %tid.y;
	// inline asm
	add.s32 	%r97, %r21, %r75;
	shl.b32 	%r98, %r97, 4;
	add.s32 	%r99, %r98, %r127;
	ld.shared.v4.f32 	{%f241, %f242, %f243, %f244}, [%r99+96];
	mad.f32 	%f245, %f27, %f241, %f225;
	mad.f32 	%f246, %f27, %f242, %f226;
	mad.f32 	%f247, %f27, %f243, %f227;
	mad.f32 	%f248, %f27, %f244, %f228;
	ld.const.f32 	%f31, [%r78+28];
	// inline asm
	mov.u32 	%r76, %tid.y;
	// inline asm
	add.s32 	%r100, %r21, %r76;
	shl.b32 	%r101, %r100, 4;
	add.s32 	%r102, %r101, %r127;
	ld.shared.v4.f32 	{%f261, %f262, %f263, %f264}, [%r102+112];
	mad.f32 	%f269, %f31, %f261, %f245;
	mad.f32 	%f270, %f31, %f262, %f246;
	mad.f32 	%f271, %f31, %f263, %f247;
	mad.f32 	%f272, %f31, %f264, %f248;
	add.s32 	%r22, %r21, 8;
	add.s32 	%r103, %r21, 16;
	ld.param.u32 	%r120, [BlurColumn_param_4];
	setp.lt.u32 	%p5, %r103, %r120;
	mov.u32 	%r135, %r22;
	@%p5 bra 	BB5_8;

	mov.u32 	%r134, %r22;

BB5_10:
	mov.u32 	%r133, %r134;
	ld.param.u32 	%r119, [BlurColumn_param_4];
	setp.lt.u32 	%p6, %r133, %r119;
	@%p6 bra 	BB5_11;
	bra.uni 	BB5_13;

BB5_11:
	shl.b32 	%r104, %r133, 2;
	ld.param.u32 	%r116, [BlurColumn_param_3];
	add.s32 	%r130, %r116, %r104;

BB5_12:
	ld.const.f32 	%f35, [%r130];
	// inline asm
	mov.u32 	%r105, %tid.y;
	// inline asm
	add.s32 	%r106, %r105, %r133;
	shl.b32 	%r107, %r106, 4;
	ld.param.u32 	%r126, [BlurColumn_param_7];
	add.s32 	%r108, %r126, %r107;
	ld.shared.v4.f32 	{%f89, %f90, %f91, %f92}, [%r108];
	mad.f32 	%f269, %f35, %f89, %f269;
	mad.f32 	%f270, %f35, %f90, %f270;
	mad.f32 	%f271, %f35, %f91, %f271;
	mad.f32 	%f272, %f35, %f92, %f272;
	add.s32 	%r130, %r130, 4;
	add.s32 	%r133, %r133, 1;
	ld.param.u32 	%r118, [BlurColumn_param_4];
	setp.lt.u32 	%p7, %r133, %r118;
	@%p7 bra 	BB5_12;

BB5_13:
	mov.f32 	%f40, 0f00000000;
	max.f32 	%f41, %f269, %f40;
	mov.f32 	%f42, 0f477FFF00;
	min.f32 	%f43, %f41, %f42;
	add.f32 	%f44, %f43, 0f3F000000;
	max.f32 	%f46, %f270, %f40;
	min.f32 	%f47, %f46, %f42;
	add.f32 	%f48, %f47, 0f3F000000;
	max.f32 	%f50, %f271, %f40;
	min.f32 	%f51, %f50, %f42;
	add.f32 	%f52, %f51, 0f3F000000;
	max.f32 	%f54, %f272, %f40;
	min.f32 	%f55, %f54, %f42;
	add.f32 	%f56, %f55, 0f3F000000;
	add.s32 	%r109, %r32, %r29;
	add.s32 	%r110, %r109, %r9;
	ld.param.u32 	%r122, [BlurColumn_param_5];
	mad.lo.s32 	%r111, %r11, %r122, %r110;
	shl.b32 	%r112, %r111, 4;
	ld.param.u32 	%r115, [BlurColumn_param_1];
	add.s32 	%r113, %r115, %r112;
	st.global.v4.f32 	[%r113], {%f44, %f48, %f52, %f56};
	ret;
}

.entry UnsharpMaskBlurColumn(
	.param .u32 .ptr .global .align 16 UnsharpMaskBlurColumn_param_0,
	.param .u32 .ptr .global .align 16 UnsharpMaskBlurColumn_param_1,
	.param .u32 .ptr .global .align 16 UnsharpMaskBlurColumn_param_2,
	.param .u32 UnsharpMaskBlurColumn_param_3,
	.param .u32 UnsharpMaskBlurColumn_param_4,
	.param .u32 .ptr .shared .align 16 UnsharpMaskBlurColumn_param_5,
	.param .u32 .ptr .shared .align 4 UnsharpMaskBlurColumn_param_6,
	.param .u32 UnsharpMaskBlurColumn_param_7,
	.param .u32 .ptr .global .align 4 UnsharpMaskBlurColumn_param_8,
	.param .u32 UnsharpMaskBlurColumn_param_9,
	.param .f32 UnsharpMaskBlurColumn_param_10,
	.param .f32 UnsharpMaskBlurColumn_param_11
)
{
	.reg .f32 	%f<369>;
	.reg .pred 	%p<27>;
	.reg .s32 	%r<175>;


	ld.param.u32 	%r5, [UnsharpMaskBlurColumn_param_4];
	ld.param.u32 	%r9, [UnsharpMaskBlurColumn_param_9];
	add.s32 	%r51, %r9, -1;
	shr.u32 	%r52, %r51, 1;
	// inline asm
	mov.u32 	%r43, %envreg0;
	// inline asm
	// inline asm
	mov.u32 	%r44, %ctaid.x;
	// inline asm
	add.s32 	%r10, %r44, %r43;
	// inline asm
	mov.u32 	%r45, %envreg1;
	// inline asm
	// inline asm
	mov.u32 	%r46, %ctaid.y;
	// inline asm
	add.s32 	%r53, %r46, %r45;
	// inline asm
	mov.u32 	%r47, %ntid.y;
	// inline asm
	mul.lo.s32 	%r54, %r53, %r47;
	sub.s32 	%r11, %r54, %r52;
	// inline asm
	mov.u32 	%r48, %envreg1;
	// inline asm
	// inline asm
	mov.u32 	%r49, %ctaid.y;
	// inline asm
	add.s32 	%r55, %r48, %r49;
	add.s32 	%r56, %r55, 1;
	// inline asm
	mov.u32 	%r50, %ntid.y;
	// inline asm
	mad.lo.s32 	%r57, %r56, %r50, %r52;
	setp.gt.s32 	%p1, %r11, -1;
	setp.lt.u32 	%p2, %r57, %r5;
	and.pred  	%p3, %p1, %p2;
	sub.s32 	%r12, %r57, %r11;
	@%p3 bra 	BB6_4;

	// inline asm
	mov.u32 	%r58, %tid.y;
	// inline asm
	setp.ge.s32 	%p4, %r58, %r12;
	mov.u32 	%r162, %r58;
	@%p4 bra 	BB6_7;

	ld.param.u32 	%r147, [UnsharpMaskBlurColumn_param_4];
	add.s32 	%r14, %r147, -1;

BB6_3:
	add.s32 	%r60, %r162, %r11;
	mov.u32 	%r61, 0;
	// inline asm
	max.s32 	%r59, %r60, %r61;
	// inline asm
	// inline asm
	min.s32 	%r62, %r59, %r14;
	// inline asm
	ld.param.u32 	%r145, [UnsharpMaskBlurColumn_param_3];
	mad.lo.s32 	%r66, %r62, %r145, %r10;
	shl.b32 	%r67, %r66, 4;
	ld.param.u32 	%r141, [UnsharpMaskBlurColumn_param_1];
	add.s32 	%r68, %r141, %r67;
	shl.b32 	%r69, %r162, 4;
	ld.param.u32 	%r151, [UnsharpMaskBlurColumn_param_5];
	add.s32 	%r70, %r151, %r69;
	ld.global.v4.f32 	{%f355, %f356, %f357, %f358}, [%r68];
	st.shared.v4.f32 	[%r70], {%f355, %f356, %f357, %f358};
	// inline asm
	mov.u32 	%r65, %ntid.y;
	// inline asm
	add.s32 	%r162, %r65, %r162;
	setp.lt.s32 	%p5, %r162, %r12;
	@%p5 bra 	BB6_3;
	bra.uni 	BB6_7;

BB6_4:
	// inline asm
	mov.u32 	%r71, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r72, %tid.x;
	// inline asm
	setp.ge.u32 	%p6, %r72, %r12;
	mov.u32 	%r163, %r72;
	@%p6 bra 	BB6_6;

BB6_5:
	add.s32 	%r73, %r163, %r11;
	ld.param.u32 	%r144, [UnsharpMaskBlurColumn_param_3];
	mad.lo.s32 	%r74, %r73, %r144, %r10;
	shl.b32 	%r75, %r74, 4;
	ld.param.u32 	%r140, [UnsharpMaskBlurColumn_param_1];
	add.s32 	%r76, %r140, %r75;
	shl.b32 	%r77, %r163, 4;
	ld.param.u32 	%r150, [UnsharpMaskBlurColumn_param_5];
	add.s32 	%r78, %r150, %r77;
	ld.global.v4.f32 	{%f351, %f352, %f353, %f354}, [%r76];
	st.shared.v4.f32 	[%r78], {%f351, %f352, %f353, %f354};
	add.s32 	%r163, %r163, %r71;
	setp.lt.u32 	%p7, %r163, %r12;
	@%p7 bra 	BB6_5;

BB6_6:
	membar.gl;

BB6_7:
	bar.sync 	0;
	// inline asm
	mov.u32 	%r79, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r80, %tid.x;
	// inline asm
	ld.param.u32 	%r161, [UnsharpMaskBlurColumn_param_9];
	setp.ge.u32 	%p8, %r80, %r161;
	mov.u32 	%r164, %r80;
	@%p8 bra 	BB6_9;

BB6_8:
	shl.b32 	%r81, %r164, 2;
	ld.param.u32 	%r154, [UnsharpMaskBlurColumn_param_6];
	add.s32 	%r82, %r154, %r81;
	ld.param.u32 	%r155, [UnsharpMaskBlurColumn_param_8];
	add.s32 	%r83, %r155, %r81;
	ld.global.f32 	%f20, [%r83];
	st.shared.f32 	[%r82], %f20;
	add.s32 	%r164, %r164, %r79;
	ld.param.u32 	%r160, [UnsharpMaskBlurColumn_param_9];
	setp.lt.u32 	%p9, %r164, %r160;
	@%p9 bra 	BB6_8;

BB6_9:
	membar.gl;
	bar.sync 	0;
	// inline asm
	mov.u32 	%r84, %envreg4;
	// inline asm
	// inline asm
	mov.u32 	%r85, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r86, %ctaid.y;
	// inline asm
	// inline asm
	mov.u32 	%r87, %tid.y;
	// inline asm
	add.s32 	%r88, %r87, %r84;
	mad.lo.s32 	%r25, %r86, %r85, %r88;
	ld.param.u32 	%r146, [UnsharpMaskBlurColumn_param_4];
	setp.lt.u32 	%p10, %r25, %r146;
	@%p10 bra 	BB6_11;

	ret;

BB6_11:
	ld.param.u32 	%r159, [UnsharpMaskBlurColumn_param_9];
	setp.gt.u32 	%p11, %r159, 8;
	@%p11 bra 	BB6_13;

	mov.f32 	%f21, 0f00000000;
	mov.f32 	%f365, %f21;
	mov.f32 	%f366, %f21;
	mov.f32 	%f367, %f21;
	mov.f32 	%f368, %f21;
	mov.u32 	%r169, 0;
	bra.uni 	BB6_16;

BB6_13:
	mov.f32 	%f22, 0f00000000;
	mov.f32 	%f365, %f22;
	mov.f32 	%f366, %f22;
	mov.f32 	%f367, %f22;
	mov.f32 	%f368, %f22;
	mov.u32 	%r170, 0;

BB6_14:
	mov.u32 	%r26, %r170;
	shl.b32 	%r99, %r26, 2;
	ld.param.u32 	%r153, [UnsharpMaskBlurColumn_param_6];
	add.s32 	%r100, %r153, %r99;
	ld.shared.f32 	%f23, [%r100];
	// inline asm
	mov.u32 	%r91, %tid.y;
	// inline asm
	add.s32 	%r101, %r91, %r26;
	shl.b32 	%r102, %r101, 4;
	ld.param.u32 	%r149, [UnsharpMaskBlurColumn_param_5];
	add.s32 	%r103, %r149, %r102;
	ld.shared.v4.f32 	{%f207, %f208, %f209, %f210}, [%r103];
	mad.f32 	%f211, %f23, %f207, %f365;
	mad.f32 	%f212, %f23, %f208, %f366;
	mad.f32 	%f213, %f23, %f209, %f367;
	mad.f32 	%f214, %f23, %f210, %f368;
	ld.shared.f32 	%f27, [%r100+4];
	// inline asm
	mov.u32 	%r92, %tid.y;
	// inline asm
	add.s32 	%r104, %r26, %r92;
	shl.b32 	%r105, %r104, 4;
	add.s32 	%r106, %r105, %r149;
	ld.shared.v4.f32 	{%f227, %f228, %f229, %f230}, [%r106+16];
	mad.f32 	%f231, %f27, %f227, %f211;
	mad.f32 	%f232, %f27, %f228, %f212;
	mad.f32 	%f233, %f27, %f229, %f213;
	mad.f32 	%f234, %f27, %f230, %f214;
	ld.shared.f32 	%f31, [%r100+8];
	// inline asm
	mov.u32 	%r93, %tid.y;
	// inline asm
	add.s32 	%r107, %r26, %r93;
	shl.b32 	%r108, %r107, 4;
	add.s32 	%r109, %r108, %r149;
	ld.shared.v4.f32 	{%f247, %f248, %f249, %f250}, [%r109+32];
	mad.f32 	%f251, %f31, %f247, %f231;
	mad.f32 	%f252, %f31, %f248, %f232;
	mad.f32 	%f253, %f31, %f249, %f233;
	mad.f32 	%f254, %f31, %f250, %f234;
	ld.shared.f32 	%f35, [%r100+12];
	// inline asm
	mov.u32 	%r94, %tid.y;
	// inline asm
	add.s32 	%r110, %r26, %r94;
	shl.b32 	%r111, %r110, 4;
	add.s32 	%r112, %r111, %r149;
	ld.shared.v4.f32 	{%f267, %f268, %f269, %f270}, [%r112+48];
	mad.f32 	%f271, %f35, %f267, %f251;
	mad.f32 	%f272, %f35, %f268, %f252;
	mad.f32 	%f273, %f35, %f269, %f253;
	mad.f32 	%f274, %f35, %f270, %f254;
	ld.shared.f32 	%f39, [%r100+16];
	// inline asm
	mov.u32 	%r95, %tid.y;
	// inline asm
	add.s32 	%r113, %r26, %r95;
	shl.b32 	%r114, %r113, 4;
	add.s32 	%r115, %r114, %r149;
	ld.shared.v4.f32 	{%f287, %f288, %f289, %f290}, [%r115+64];
	mad.f32 	%f291, %f39, %f287, %f271;
	mad.f32 	%f292, %f39, %f288, %f272;
	mad.f32 	%f293, %f39, %f289, %f273;
	mad.f32 	%f294, %f39, %f290, %f274;
	ld.shared.f32 	%f43, [%r100+20];
	// inline asm
	mov.u32 	%r96, %tid.y;
	// inline asm
	add.s32 	%r116, %r26, %r96;
	shl.b32 	%r117, %r116, 4;
	add.s32 	%r118, %r117, %r149;
	ld.shared.v4.f32 	{%f307, %f308, %f309, %f310}, [%r118+80];
	mad.f32 	%f311, %f43, %f307, %f291;
	mad.f32 	%f312, %f43, %f308, %f292;
	mad.f32 	%f313, %f43, %f309, %f293;
	mad.f32 	%f314, %f43, %f310, %f294;
	ld.shared.f32 	%f47, [%r100+24];
	// inline asm
	mov.u32 	%r97, %tid.y;
	// inline asm
	add.s32 	%r119, %r26, %r97;
	shl.b32 	%r120, %r119, 4;
	add.s32 	%r121, %r120, %r149;
	ld.shared.v4.f32 	{%f327, %f328, %f329, %f330}, [%r121+96];
	mad.f32 	%f331, %f47, %f327, %f311;
	mad.f32 	%f332, %f47, %f328, %f312;
	mad.f32 	%f333, %f47, %f329, %f313;
	mad.f32 	%f334, %f47, %f330, %f314;
	ld.shared.f32 	%f51, [%r100+28];
	// inline asm
	mov.u32 	%r98, %tid.y;
	// inline asm
	add.s32 	%r122, %r26, %r98;
	shl.b32 	%r123, %r122, 4;
	add.s32 	%r124, %r123, %r149;
	ld.shared.v4.f32 	{%f347, %f348, %f349, %f350}, [%r124+112];
	mad.f32 	%f365, %f51, %f347, %f331;
	mad.f32 	%f366, %f51, %f348, %f332;
	mad.f32 	%f367, %f51, %f349, %f333;
	mad.f32 	%f368, %f51, %f350, %f334;
	add.s32 	%r27, %r26, 8;
	add.s32 	%r125, %r26, 16;
	ld.param.u32 	%r158, [UnsharpMaskBlurColumn_param_9];
	setp.lt.u32 	%p12, %r125, %r158;
	mov.u32 	%r170, %r27;
	@%p12 bra 	BB6_14;

	mov.u32 	%r169, %r27;

BB6_16:
	mov.u32 	%r168, %r169;
	ld.param.u32 	%r157, [UnsharpMaskBlurColumn_param_9];
	setp.lt.u32 	%p13, %r168, %r157;
	@%p13 bra 	BB6_17;
	bra.uni 	BB6_19;

BB6_17:
	shl.b32 	%r126, %r168, 2;
	ld.param.u32 	%r152, [UnsharpMaskBlurColumn_param_6];
	add.s32 	%r165, %r152, %r126;

BB6_18:
	ld.shared.f32 	%f55, [%r165];
	// inline asm
	mov.u32 	%r127, %tid.y;
	// inline asm
	add.s32 	%r128, %r127, %r168;
	shl.b32 	%r129, %r128, 4;
	ld.param.u32 	%r148, [UnsharpMaskBlurColumn_param_5];
	add.s32 	%r130, %r148, %r129;
	ld.shared.v4.f32 	{%f175, %f176, %f177, %f178}, [%r130];
	mad.f32 	%f365, %f55, %f175, %f365;
	mad.f32 	%f366, %f55, %f176, %f366;
	mad.f32 	%f367, %f55, %f177, %f367;
	mad.f32 	%f368, %f55, %f178, %f368;
	add.s32 	%r165, %r165, 4;
	add.s32 	%r168, %r168, 1;
	ld.param.u32 	%r156, [UnsharpMaskBlurColumn_param_9];
	setp.lt.u32 	%p14, %r168, %r156;
	@%p14 bra 	BB6_18;

BB6_19:
	mov.f32 	%f76, 0f00000000;
	max.f32 	%f77, %f365, %f76;
	mov.f32 	%f78, 0f477FFF00;
	min.f32 	%f79, %f77, %f78;
	add.f32 	%f60, %f79, 0f3F000000;
	max.f32 	%f81, %f366, %f76;
	min.f32 	%f82, %f81, %f78;
	add.f32 	%f62, %f82, 0f3F000000;
	max.f32 	%f84, %f367, %f76;
	min.f32 	%f85, %f84, %f78;
	add.f32 	%f64, %f85, 0f3F000000;
	max.f32 	%f87, %f368, %f76;
	min.f32 	%f88, %f87, %f78;
	add.f32 	%f66, %f88, 0f3F000000;
	// inline asm
	cvt.rmi.f32.f32 	%f59, %f60;
	// inline asm
	// inline asm
	cvt.rmi.f32.f32 	%f61, %f62;
	// inline asm
	// inline asm
	cvt.rmi.f32.f32 	%f63, %f64;
	// inline asm
	// inline asm
	cvt.rmi.f32.f32 	%f65, %f66;
	// inline asm
	ld.param.u32 	%r143, [UnsharpMaskBlurColumn_param_3];
	mad.lo.s32 	%r34, %r25, %r143, %r10;
	shl.b32 	%r131, %r34, 4;
	ld.param.u32 	%r139, [UnsharpMaskBlurColumn_param_0];
	add.s32 	%r132, %r139, %r131;
	ld.global.v4.f32 	{%f115, %f116, %f117, %f118}, [%r132];
	sub.f32 	%f131, %f115, %f59;
	sub.f32 	%f132, %f116, %f61;
	sub.f32 	%f133, %f117, %f63;
	sub.f32 	%f134, %f118, %f65;
	mov.f32 	%f89, 0f40000000;
	mul.f32 	%f155, %f131, %f89;
	mul.f32 	%f156, %f132, %f89;
	mul.f32 	%f157, %f133, %f89;
	mul.f32 	%f158, %f134, %f89;
	// inline asm
	abs.f32 	%f67, %f155;
	// inline asm
	// inline asm
	abs.f32 	%f69, %f156;
	// inline asm
	// inline asm
	abs.f32 	%f71, %f157;
	// inline asm
	// inline asm
	abs.f32 	%f73, %f158;
	// inline asm
	ld.param.f32 	%f360, [UnsharpMaskBlurColumn_param_11];
	mul.f32 	%f7, %f360, 0f477FFF00;
	setp.nan.f32 	%p15, %f67, %f7;
	@%p15 bra 	BB6_21;

	setp.lt.f32 	%p16, %f67, %f7;
	selp.b32 	%r171, -1, 0, %p16;
	bra.uni 	BB6_22;

BB6_21:
	mov.u32 	%r171, 0;

BB6_22:
	setp.nan.f32 	%p17, %f69, %f7;
	@%p17 bra 	BB6_24;

	setp.lt.f32 	%p18, %f69, %f7;
	selp.b32 	%r172, -1, 0, %p18;
	bra.uni 	BB6_25;

BB6_24:
	mov.u32 	%r172, 0;

BB6_25:
	setp.nan.f32 	%p19, %f71, %f7;
	@%p19 bra 	BB6_27;

	setp.lt.f32 	%p20, %f71, %f7;
	selp.b32 	%r173, -1, 0, %p20;
	bra.uni 	BB6_28;

BB6_27:
	mov.u32 	%r173, 0;

BB6_28:
	setp.nan.f32 	%p21, %f73, %f7;
	@%p21 bra 	BB6_30;

	setp.lt.f32 	%p22, %f73, %f7;
	selp.b32 	%r174, -1, 0, %p22;
	bra.uni 	BB6_31;

BB6_30:
	mov.u32 	%r174, 0;

BB6_31:
	ld.param.f32 	%f359, [UnsharpMaskBlurColumn_param_10];
	mad.f32 	%f111, %f131, %f359, %f115;
	mad.f32 	%f112, %f132, %f359, %f116;
	mad.f32 	%f113, %f133, %f359, %f117;
	mad.f32 	%f114, %f134, %f359, %f118;
	setp.gt.s32 	%p23, %r171, -1;
	@%p23 bra 	BB6_33;

	mov.f32 	%f361, %f115;
	bra.uni 	BB6_34;

BB6_33:
	mov.f32 	%f361, %f111;

BB6_34:
	setp.gt.s32 	%p24, %r172, -1;
	@%p24 bra 	BB6_36;

	mov.f32 	%f362, %f116;
	bra.uni 	BB6_37;

BB6_36:
	mov.f32 	%f362, %f112;

BB6_37:
	setp.gt.s32 	%p25, %r173, -1;
	@%p25 bra 	BB6_39;

	mov.f32 	%f363, %f117;
	bra.uni 	BB6_40;

BB6_39:
	mov.f32 	%f363, %f113;

BB6_40:
	setp.gt.s32 	%p26, %r174, -1;
	@%p26 bra 	BB6_42;

	mov.f32 	%f364, %f118;
	bra.uni 	BB6_43;

BB6_42:
	mov.f32 	%f364, %f114;

BB6_43:
	max.f32 	%f94, %f361, %f76;
	min.f32 	%f96, %f94, %f78;
	add.f32 	%f97, %f96, 0f3F000000;
	max.f32 	%f98, %f362, %f76;
	min.f32 	%f99, %f98, %f78;
	add.f32 	%f100, %f99, 0f3F000000;
	max.f32 	%f101, %f363, %f76;
	min.f32 	%f102, %f101, %f78;
	add.f32 	%f103, %f102, 0f3F000000;
	max.f32 	%f104, %f364, %f76;
	min.f32 	%f105, %f104, %f78;
	add.f32 	%f106, %f105, 0f3F000000;
	ld.param.u32 	%r142, [UnsharpMaskBlurColumn_param_2];
	add.s32 	%r138, %r142, %r131;
	st.global.v4.f32 	[%r138], {%f97, %f100, %f103, %f106};
	ret;
}

.entry HullPass1(
	.param .u32 .ptr .global .align 16 HullPass1_param_0,
	.param .u32 .ptr .global .align 16 HullPass1_param_1,
	.param .u32 HullPass1_param_2,
	.param .u32 HullPass1_param_3,
	.param .align 8 .b8 HullPass1_param_4[8],
	.param .u32 HullPass1_param_5,
	.param .u32 HullPass1_param_6
)
{
	.reg .f32 	%f<107>;
	.reg .pred 	%p<14>;
	.reg .s32 	%r<62>;


	ld.param.u32 	%r1, [HullPass1_param_0];
	ld.param.u32 	%r3, [HullPass1_param_2];
	ld.param.u32 	%r36, [HullPass1_param_3];
	ld.param.v2.u32 	{%r55, %r56}, [HullPass1_param_4];
	// inline asm
	mov.u32 	%r16, %envreg3;
	// inline asm
	// inline asm
	mov.u32 	%r17, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r18, %ctaid.x;
	// inline asm
	// inline asm
	mov.u32 	%r19, %tid.x;
	// inline asm
	add.s32 	%r37, %r19, %r16;
	mad.lo.s32 	%r38, %r18, %r17, %r37;
	// inline asm
	mov.u32 	%r20, %envreg4;
	// inline asm
	// inline asm
	mov.u32 	%r21, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r22, %ctaid.y;
	// inline asm
	// inline asm
	mov.u32 	%r23, %tid.y;
	// inline asm
	add.s32 	%r39, %r23, %r20;
	mad.lo.s32 	%r40, %r22, %r21, %r39;
	mad.lo.s32 	%r6, %r40, %r3, %r38;
	shl.b32 	%r41, %r6, 4;
	add.s32 	%r42, %r1, %r41;
	ld.global.v4.f32 	{%f75, %f76, %f77, %f78}, [%r42];
	add.s32 	%r31, %r40, %r56;
	mov.u32 	%r32, 0;
	add.s32 	%r25, %r38, %r55;
	// inline asm
	max.s32 	%r24, %r25, %r32;
	// inline asm
	add.s32 	%r29, %r3, -1;
	// inline asm
	min.s32 	%r27, %r24, %r29;
	// inline asm
	// inline asm
	max.s32 	%r30, %r31, %r32;
	// inline asm
	add.s32 	%r35, %r36, -1;
	// inline asm
	min.s32 	%r33, %r30, %r35;
	// inline asm
	setp.eq.s32 	%p1, %r27, %r25;
	setp.eq.s32 	%p2, %r33, %r31;
	and.pred  	%p3, %p1, %p2;
	@%p3 bra 	BB7_2;

	mov.f32 	%f17, 0f00000000;
	mov.f32 	%f103, %f17;
	mov.f32 	%f104, %f17;
	mov.f32 	%f105, %f17;
	mov.f32 	%f106, %f17;
	bra.uni 	BB7_3;

BB7_2:
	ld.param.u32 	%r59, [HullPass1_param_2];
	mad.lo.s32 	%r45, %r33, %r59, %r27;
	shl.b32 	%r46, %r45, 4;
	ld.param.u32 	%r57, [HullPass1_param_0];
	add.s32 	%r47, %r57, %r46;
	ld.global.v4.f32 	{%f103, %f104, %f105, %f106}, [%r47];

BB7_3:
	cvt.rzi.s32.f32 	%r48, %f75;
	cvt.rzi.s32.f32 	%r9, %f76;
	cvt.rzi.s32.f32 	%r10, %f77;
	cvt.rzi.s32.f32 	%r11, %f78;
	cvt.rzi.s32.f32 	%r49, %f103;
	cvt.rzi.s32.f32 	%r12, %f104;
	cvt.rzi.s32.f32 	%r13, %f105;
	cvt.rzi.s32.f32 	%r14, %f106;
	mov.f32 	%f26, 0f43808000;
	mul.f32 	%f1, %f26, 0f40000000;
	mul.f32 	%f2, %f26, 0f3F800000;
	cvt.rn.f32.s32 	%f3, %r49;
	cvt.rn.f32.s32 	%f4, %r48;
	ld.param.u32 	%r60, [HullPass1_param_5];
	setp.gt.s32 	%p4, %r60, 0;
	@%p4 bra 	BB7_5;

	sub.f32 	%f27, %f4, %f1;
	setp.gtu.f32 	%p5, %f3, %f27;
	sub.f32 	%f28, %f4, %f2;
	selp.f32 	%f98, %f4, %f28, %p5;
	cvt.rn.f32.s32 	%f29, %r9;
	sub.f32 	%f30, %f29, %f1;
	cvt.rn.f32.s32 	%f31, %r12;
	setp.gtu.f32 	%p6, %f31, %f30;
	sub.f32 	%f32, %f29, %f2;
	selp.f32 	%f97, %f29, %f32, %p6;
	cvt.rn.f32.s32 	%f33, %r10;
	sub.f32 	%f34, %f33, %f1;
	cvt.rn.f32.s32 	%f35, %r13;
	setp.gtu.f32 	%p7, %f35, %f34;
	sub.f32 	%f36, %f33, %f2;
	selp.f32 	%f96, %f33, %f36, %p7;
	cvt.rn.f32.s32 	%f37, %r11;
	sub.f32 	%f38, %f37, %f1;
	cvt.rn.f32.s32 	%f39, %r14;
	setp.gtu.f32 	%p8, %f39, %f38;
	sub.f32 	%f40, %f37, %f2;
	selp.f32 	%f95, %f37, %f40, %p8;
	bra.uni 	BB7_6;

BB7_5:
	add.f32 	%f41, %f4, %f1;
	setp.ltu.f32 	%p9, %f3, %f41;
	add.f32 	%f42, %f4, %f2;
	selp.f32 	%f98, %f4, %f42, %p9;
	cvt.rn.f32.s32 	%f43, %r9;
	add.f32 	%f44, %f43, %f1;
	cvt.rn.f32.s32 	%f45, %r12;
	setp.ltu.f32 	%p10, %f45, %f44;
	add.f32 	%f46, %f43, %f2;
	selp.f32 	%f97, %f43, %f46, %p10;
	cvt.rn.f32.s32 	%f47, %r10;
	add.f32 	%f48, %f47, %f1;
	cvt.rn.f32.s32 	%f49, %r13;
	setp.ltu.f32 	%p11, %f49, %f48;
	add.f32 	%f50, %f47, %f2;
	selp.f32 	%f96, %f47, %f50, %p11;
	cvt.rn.f32.s32 	%f51, %r11;
	add.f32 	%f52, %f51, %f1;
	cvt.rn.f32.s32 	%f53, %r14;
	setp.ltu.f32 	%p12, %f53, %f52;
	add.f32 	%f54, %f51, %f2;
	selp.f32 	%f95, %f51, %f54, %p12;

BB7_6:
	cvt.rzi.s32.f32 	%r15, %f95;
	cvt.rzi.s32.f32 	%r50, %f98;
	cvt.rn.f32.s32 	%f55, %r50;
	cvt.rzi.s32.f32 	%r51, %f97;
	cvt.rn.f32.s32 	%f56, %r51;
	cvt.rzi.s32.f32 	%r52, %f96;
	cvt.rn.f32.s32 	%f57, %r52;
	mov.f32 	%f99, %f55;
	mov.f32 	%f100, %f56;
	mov.f32 	%f101, %f57;
	mov.f32 	%f102, %f78;
	ld.param.u32 	%r61, [HullPass1_param_6];
	setp.eq.s32 	%p13, %r61, 0;
	@%p13 bra 	BB7_8;

	cvt.rn.f32.s32 	%f58, %r15;
	mov.f32 	%f99, %f55;
	mov.f32 	%f100, %f56;
	mov.f32 	%f101, %f57;
	mov.f32 	%f102, %f58;

BB7_8:
	ld.param.u32 	%r58, [HullPass1_param_1];
	add.s32 	%r54, %r58, %r41;
	st.global.v4.f32 	[%r54], {%f99, %f100, %f101, %f102};
	ret;
}

.entry HullPass2(
	.param .u32 .ptr .global .align 16 HullPass2_param_0,
	.param .u32 .ptr .global .align 16 HullPass2_param_1,
	.param .u32 HullPass2_param_2,
	.param .u32 HullPass2_param_3,
	.param .align 8 .b8 HullPass2_param_4[8],
	.param .u32 HullPass2_param_5,
	.param .u32 HullPass2_param_6
)
{
	.reg .f32 	%f<128>;
	.reg .pred 	%p<33>;
	.reg .s32 	%r<103>;


	ld.param.u32 	%r1, [HullPass2_param_0];
	ld.param.u32 	%r3, [HullPass2_param_2];
	ld.param.u32 	%r49, [HullPass2_param_3];
	ld.param.v2.u32 	{%r94, %r95}, [HullPass2_param_4];
	// inline asm
	mov.u32 	%r29, %envreg3;
	// inline asm
	// inline asm
	mov.u32 	%r30, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r31, %ctaid.x;
	// inline asm
	// inline asm
	mov.u32 	%r32, %tid.x;
	// inline asm
	add.s32 	%r50, %r32, %r29;
	mad.lo.s32 	%r6, %r31, %r30, %r50;
	// inline asm
	mov.u32 	%r33, %envreg4;
	// inline asm
	// inline asm
	mov.u32 	%r34, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r35, %ctaid.y;
	// inline asm
	// inline asm
	mov.u32 	%r36, %tid.y;
	// inline asm
	add.s32 	%r51, %r36, %r33;
	mad.lo.s32 	%r7, %r35, %r34, %r51;
	mad.lo.s32 	%r8, %r7, %r3, %r6;
	shl.b32 	%r52, %r8, 4;
	add.s32 	%r53, %r1, %r52;
	ld.global.v4.f32 	{%f80, %f81, %f82, %f83}, [%r53];
	add.s32 	%r44, %r7, %r95;
	mov.u32 	%r45, 0;
	add.s32 	%r38, %r6, %r94;
	// inline asm
	max.s32 	%r37, %r38, %r45;
	// inline asm
	add.s32 	%r42, %r3, -1;
	// inline asm
	min.s32 	%r40, %r37, %r42;
	// inline asm
	// inline asm
	max.s32 	%r43, %r44, %r45;
	// inline asm
	add.s32 	%r48, %r49, -1;
	// inline asm
	min.s32 	%r46, %r43, %r48;
	// inline asm
	setp.eq.s32 	%p1, %r40, %r38;
	setp.eq.s32 	%p2, %r46, %r44;
	and.pred  	%p3, %p1, %p2;
	@%p3 bra 	BB8_2;

	mov.f32 	%f17, 0f00000000;
	mov.f32 	%f124, %f17;
	mov.f32 	%f125, %f17;
	mov.f32 	%f126, %f17;
	mov.f32 	%f127, %f17;
	bra.uni 	BB8_3;

BB8_2:
	ld.param.u32 	%r99, [HullPass2_param_2];
	mad.lo.s32 	%r54, %r46, %r99, %r40;
	shl.b32 	%r55, %r54, 4;
	ld.param.u32 	%r97, [HullPass2_param_0];
	add.s32 	%r56, %r97, %r55;
	ld.global.v4.f32 	{%f124, %f125, %f126, %f127}, [%r56];

BB8_3:
	sub.s32 	%r58, %r6, %r94;
	// inline asm
	max.s32 	%r57, %r58, %r45;
	// inline asm
	// inline asm
	min.s32 	%r60, %r57, %r42;
	// inline asm
	sub.s32 	%r64, %r7, %r95;
	// inline asm
	max.s32 	%r63, %r64, %r45;
	// inline asm
	// inline asm
	min.s32 	%r66, %r63, %r48;
	// inline asm
	setp.eq.s32 	%p4, %r60, %r58;
	setp.eq.s32 	%p5, %r66, %r64;
	and.pred  	%p6, %p4, %p5;
	@%p6 bra 	BB8_5;

	mov.f32 	%f18, 0f00000000;
	mov.f32 	%f120, %f18;
	mov.f32 	%f121, %f18;
	mov.f32 	%f122, %f18;
	mov.f32 	%f123, %f18;
	bra.uni 	BB8_6;

BB8_5:
	ld.param.u32 	%r100, [HullPass2_param_2];
	mad.lo.s32 	%r69, %r66, %r100, %r60;
	shl.b32 	%r70, %r69, 4;
	ld.param.u32 	%r96, [HullPass2_param_0];
	add.s32 	%r71, %r96, %r70;
	ld.global.v4.f32 	{%f120, %f121, %f122, %f123}, [%r71];

BB8_6:
	cvt.rzi.s32.f32 	%r17, %f80;
	cvt.rzi.s32.f32 	%r18, %f81;
	cvt.rzi.s32.f32 	%r19, %f82;
	cvt.rzi.s32.f32 	%r20, %f83;
	cvt.rzi.s32.f32 	%r21, %f124;
	cvt.rzi.s32.f32 	%r22, %f125;
	cvt.rzi.s32.f32 	%r23, %f126;
	cvt.rzi.s32.f32 	%r24, %f127;
	cvt.rzi.s32.f32 	%r72, %f120;
	cvt.rzi.s32.f32 	%r25, %f121;
	cvt.rzi.s32.f32 	%r26, %f122;
	cvt.rzi.s32.f32 	%r27, %f123;
	mov.f32 	%f31, 0f43808000;
	mul.f32 	%f1, %f31, 0f40000000;
	mul.f32 	%f2, %f31, 0f3F800000;
	cvt.rn.f32.s32 	%f3, %r72;
	cvt.rn.f32.s32 	%f4, %r17;
	ld.param.u32 	%r101, [HullPass2_param_5];
	setp.gt.s32 	%p7, %r101, 0;
	@%p7 bra 	BB8_8;

	sub.f32 	%f32, %f4, %f1;
	setp.gt.f32 	%p8, %f3, %f32;
	selp.u32 	%r73, 1, 0, %p8;
	setp.ge.s32 	%p9, %r21, %r17;
	selp.b32 	%r74, -1, 0, %p9;
	setp.eq.s32 	%p10, %r73, %r74;
	sub.f32 	%f33, %f4, %f2;
	selp.f32 	%f115, %f33, %f4, %p10;
	cvt.rn.f32.s32 	%f34, %r18;
	sub.f32 	%f35, %f34, %f1;
	cvt.rn.f32.s32 	%f36, %r25;
	setp.gt.f32 	%p11, %f36, %f35;
	selp.u32 	%r75, 1, 0, %p11;
	setp.ge.s32 	%p12, %r22, %r18;
	selp.b32 	%r76, -1, 0, %p12;
	setp.eq.s32 	%p13, %r75, %r76;
	sub.f32 	%f37, %f34, %f2;
	selp.f32 	%f114, %f37, %f34, %p13;
	cvt.rn.f32.s32 	%f38, %r19;
	sub.f32 	%f39, %f38, %f1;
	cvt.rn.f32.s32 	%f40, %r26;
	setp.gt.f32 	%p14, %f40, %f39;
	selp.u32 	%r77, 1, 0, %p14;
	setp.ge.s32 	%p15, %r23, %r19;
	selp.b32 	%r78, -1, 0, %p15;
	setp.eq.s32 	%p16, %r77, %r78;
	sub.f32 	%f41, %f38, %f2;
	selp.f32 	%f113, %f41, %f38, %p16;
	cvt.rn.f32.s32 	%f42, %r20;
	sub.f32 	%f43, %f42, %f1;
	cvt.rn.f32.s32 	%f44, %r27;
	setp.gt.f32 	%p17, %f44, %f43;
	selp.u32 	%r79, 1, 0, %p17;
	setp.ge.s32 	%p18, %r24, %r20;
	selp.b32 	%r80, -1, 0, %p18;
	setp.eq.s32 	%p19, %r79, %r80;
	sub.f32 	%f45, %f42, %f2;
	selp.f32 	%f112, %f45, %f42, %p19;
	bra.uni 	BB8_9;

BB8_8:
	add.f32 	%f46, %f4, %f1;
	setp.lt.f32 	%p20, %f3, %f46;
	selp.u32 	%r81, 1, 0, %p20;
	setp.le.s32 	%p21, %r21, %r17;
	selp.b32 	%r82, -1, 0, %p21;
	setp.eq.s32 	%p22, %r81, %r82;
	add.f32 	%f47, %f4, %f2;
	selp.f32 	%f115, %f47, %f4, %p22;
	cvt.rn.f32.s32 	%f48, %r18;
	add.f32 	%f49, %f48, %f1;
	cvt.rn.f32.s32 	%f50, %r25;
	setp.lt.f32 	%p23, %f50, %f49;
	selp.u32 	%r83, 1, 0, %p23;
	setp.le.s32 	%p24, %r22, %r18;
	selp.b32 	%r84, -1, 0, %p24;
	setp.eq.s32 	%p25, %r83, %r84;
	add.f32 	%f51, %f48, %f2;
	selp.f32 	%f114, %f51, %f48, %p25;
	cvt.rn.f32.s32 	%f52, %r19;
	add.f32 	%f53, %f52, %f1;
	cvt.rn.f32.s32 	%f54, %r26;
	setp.lt.f32 	%p26, %f54, %f53;
	selp.u32 	%r85, 1, 0, %p26;
	setp.le.s32 	%p27, %r23, %r19;
	selp.b32 	%r86, -1, 0, %p27;
	setp.eq.s32 	%p28, %r85, %r86;
	add.f32 	%f55, %f52, %f2;
	selp.f32 	%f113, %f55, %f52, %p28;
	cvt.rn.f32.s32 	%f56, %r20;
	add.f32 	%f57, %f56, %f1;
	cvt.rn.f32.s32 	%f58, %r27;
	setp.lt.f32 	%p29, %f58, %f57;
	selp.u32 	%r87, 1, 0, %p29;
	setp.le.s32 	%p30, %r24, %r20;
	selp.b32 	%r88, -1, 0, %p30;
	setp.eq.s32 	%p31, %r87, %r88;
	add.f32 	%f59, %f56, %f2;
	selp.f32 	%f112, %f59, %f56, %p31;

BB8_9:
	cvt.rzi.s32.f32 	%r28, %f112;
	cvt.rzi.s32.f32 	%r89, %f115;
	cvt.rn.f32.s32 	%f60, %r89;
	cvt.rzi.s32.f32 	%r90, %f114;
	cvt.rn.f32.s32 	%f61, %r90;
	cvt.rzi.s32.f32 	%r91, %f113;
	cvt.rn.f32.s32 	%f62, %r91;
	mov.f32 	%f116, %f60;
	mov.f32 	%f117, %f61;
	mov.f32 	%f118, %f62;
	mov.f32 	%f119, %f83;
	ld.param.u32 	%r102, [HullPass2_param_6];
	setp.eq.s32 	%p32, %r102, 0;
	@%p32 bra 	BB8_11;

	cvt.rn.f32.s32 	%f63, %r28;
	mov.f32 	%f116, %f60;
	mov.f32 	%f117, %f61;
	mov.f32 	%f118, %f62;
	mov.f32 	%f119, %f63;

BB8_11:
	ld.param.u32 	%r98, [HullPass2_param_1];
	add.s32 	%r93, %r98, %r52;
	st.global.v4.f32 	[%r93], {%f116, %f117, %f118, %f119};
	ret;
}

.entry RadialBlur(
	.param .u32 .ptr .global .align 16 RadialBlur_param_0,
	.param .u32 .ptr .global .align 16 RadialBlur_param_1,
	.param .align 16 .b8 RadialBlur_param_2[16],
	.param .u32 RadialBlur_param_3,
	.param .u32 RadialBlur_param_4,
	.param .align 8 .b8 RadialBlur_param_5[8],
	.param .u32 .ptr .const .align 4 RadialBlur_param_6,
	.param .u32 .ptr .const .align 4 RadialBlur_param_7,
	.param .u32 RadialBlur_param_8
)
{
	.reg .f32 	%f<231>;
	.reg .pred 	%p<28>;
	.reg .s32 	%r<98>;


	ld.param.v2.f32 	{%f211, %f212}, [RadialBlur_param_5];
	ld.param.v4.f32 	{%f227, %f228, %f229, %f230}, [RadialBlur_param_2];
	// inline asm
	mov.u32 	%r22, %envreg3;
	// inline asm
	// inline asm
	mov.u32 	%r23, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r24, %ctaid.x;
	// inline asm
	// inline asm
	mov.u32 	%r25, %tid.x;
	// inline asm
	add.s32 	%r34, %r25, %r22;
	mad.lo.s32 	%r8, %r24, %r23, %r34;
	// inline asm
	mov.u32 	%r26, %envreg4;
	// inline asm
	// inline asm
	mov.u32 	%r27, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r28, %ctaid.y;
	// inline asm
	// inline asm
	mov.u32 	%r29, %tid.y;
	// inline asm
	add.s32 	%r35, %r29, %r26;
	mad.lo.s32 	%r9, %r28, %r27, %r35;
	// inline asm
	mov.u32 	%r30, %envreg6;
	// inline asm
	// inline asm
	mov.u32 	%r31, %ntid.x;
	// inline asm
	mul.lo.s32 	%r10, %r31, %r30;
	// inline asm
	mov.u32 	%r32, %envreg7;
	// inline asm
	// inline asm
	mov.u32 	%r33, %ntid.y;
	// inline asm
	mul.lo.s32 	%r11, %r33, %r32;
	cvt.rn.f32.s32 	%f47, %r8;
	sub.f32 	%f42, %f47, %f211;
	cvt.rn.f32.s32 	%f48, %r9;
	sub.f32 	%f44, %f48, %f212;
	// inline asm
	abs.f32 	%f41, %f42;
	// inline asm
	// inline asm
	abs.f32 	%f43, %f44;
	// inline asm
	setp.gt.f32 	%p2, %f41, %f43;
	selp.f32 	%f5, %f43, %f41, %p2;
	selp.f32 	%f46, %f41, %f43, %p2;
	// inline asm
	abs.f32 	%f45, %f46;
	// inline asm
	setp.gt.f32 	%p3, %f45, 0f7E800000;
	mov.f32 	%f213, %f46;
	@%p3 bra 	BB9_2;

	mov.f32 	%f214, %f5;
	bra.uni 	BB9_3;

BB9_2:
	mov.f32 	%f49, 0f3E800000;
	mul.rn.f32 	%f7, %f5, %f49;
	mul.rn.f32 	%f213, %f46, %f49;
	mov.f32 	%f214, %f7;

BB9_3:
	mov.f32 	%f10, %f214;
	// inline asm
	div.approx.f32 	%f50, %f10, %f213;
	// inline asm
	mul.rn.f32 	%f61, %f50, %f50;
	add.f32 	%f54, %f61, 0f3F800000;
	// inline asm
	sqrt.approx.f32 	%f53, %f54;
	// inline asm
	mul.rn.f32 	%f62, %f46, %f53;
	add.f32 	%f63, %f46, %f5;
	setp.eq.f32 	%p4, %f46, 0f00000000;
	selp.f32 	%f64, %f63, %f62, %p4;
	mov.f32 	%f11, 0f7F800000;
	setp.eq.f32 	%p5, %f46, 0f7F800000;
	setp.eq.f32 	%p6, %f5, 0f7F800000;
	or.pred  	%p7, %p5, %p6;
	selp.f32 	%f12, 0f7F800000, %f64, %p7;
	// inline asm
	abs.f32 	%f55, %f211;
	// inline asm
	// inline asm
	abs.f32 	%f57, %f212;
	// inline asm
	setp.gt.f32 	%p8, %f55, %f57;
	selp.f32 	%f13, %f57, %f55, %p8;
	selp.f32 	%f60, %f55, %f57, %p8;
	// inline asm
	abs.f32 	%f59, %f60;
	// inline asm
	setp.gt.f32 	%p9, %f59, 0f7E800000;
	mov.f32 	%f215, %f60;
	@%p9 bra 	BB9_5;

	mov.f32 	%f216, %f13;
	bra.uni 	BB9_6;

BB9_5:
	mov.f32 	%f65, 0f3E800000;
	mul.rn.f32 	%f15, %f13, %f65;
	mul.rn.f32 	%f215, %f60, %f65;
	mov.f32 	%f216, %f15;

BB9_6:
	mov.f32 	%f18, %f216;
	// inline asm
	div.approx.f32 	%f66, %f18, %f215;
	// inline asm
	mul.rn.f32 	%f71, %f66, %f66;
	add.f32 	%f70, %f71, 0f3F800000;
	// inline asm
	sqrt.approx.f32 	%f69, %f70;
	// inline asm
	mul.rn.f32 	%f72, %f60, %f69;
	add.f32 	%f73, %f60, %f13;
	setp.eq.f32 	%p10, %f60, 0f00000000;
	selp.f32 	%f74, %f73, %f72, %p10;
	setp.eq.f32 	%p11, %f13, %f11;
	setp.eq.f32 	%p12, %f60, %f11;
	or.pred  	%p13, %p12, %p11;
	selp.f32 	%f19, %f11, %f74, %p13;
	setp.gt.f32 	%p14, %f12, 0f00000000;
	@%p14 bra 	BB9_8;

	mov.u32 	%r95, 1;
	bra.uni 	BB9_9;

BB9_8:
	div.full.f32 	%f75, %f19, %f12;
	cvt.rzi.u32.f32 	%r37, %f75;
	setp.eq.s32 	%p15, %r37, 0;
	selp.b32 	%r38, 1, %r37, %p15;
	ld.param.u32 	%r94, [RadialBlur_param_8];
	setp.lt.u32 	%p16, %r38, %r94;
	add.s32 	%r39, %r94, -1;
	selp.b32 	%r95, %r38, %r39, %p16;

BB9_9:
	ld.param.u32 	%r85, [RadialBlur_param_3];
	and.b32  	%r40, %r85, 8;
	setp.eq.s32 	%p17, %r40, 0;
	ld.param.u32 	%r86, [RadialBlur_param_4];
	setp.eq.s32 	%p18, %r86, 0;
	or.pred  	%p19, %p17, %p18;
	ld.param.u32 	%r93, [RadialBlur_param_8];
	setp.eq.s32 	%p1, %r93, 0;
	@%p19 bra 	BB9_21;

	@%p1 bra 	BB9_13;

	add.s32 	%r14, %r10, -1;
	add.s32 	%r15, %r11, -1;
	mov.f32 	%f218, 0f00000000;
	mov.f32 	%f217, %f218;
	mov.u32 	%r41, 0;
	mov.u32 	%r96, %r41;

BB9_12:
	mov.u32 	%r16, %r96;
	shl.b32 	%r54, %r16, 2;
	ld.param.u32 	%r88, [RadialBlur_param_6];
	add.s32 	%r55, %r88, %r54;
	ld.const.f32 	%f78, [%r55];
	mad.f32 	%f79, %f42, %f78, %f211;
	ld.param.u32 	%r90, [RadialBlur_param_7];
	add.s32 	%r56, %r90, %r54;
	ld.const.f32 	%f80, [%r56];
	mul.f32 	%f81, %f44, %f80;
	sub.f32 	%f82, %f79, %f81;
	add.f32 	%f83, %f82, 0f3F000000;
	cvt.rzi.s32.f32 	%r43, %f83;
	// inline asm
	max.s32 	%r42, %r43, %r41;
	// inline asm
	// inline asm
	min.s32 	%r45, %r42, %r14;
	// inline asm
	mad.f32 	%f84, %f42, %f80, %f212;
	mad.f32 	%f85, %f44, %f78, %f84;
	add.f32 	%f86, %f85, 0f3F000000;
	cvt.rzi.s32.f32 	%r49, %f86;
	// inline asm
	max.s32 	%r48, %r49, %r41;
	// inline asm
	// inline asm
	min.s32 	%r51, %r48, %r15;
	// inline asm
	mad.lo.s32 	%r57, %r51, %r10, %r45;
	shl.b32 	%r58, %r57, 4;
	ld.param.u32 	%r83, [RadialBlur_param_0];
	add.s32 	%r59, %r83, %r58;
	ld.global.v4.f32 	{%f207, %f208, %f209, %f210}, [%r59];
	mov.f32 	%f88, 0f477FFF00;
	sub.f32 	%f89, %f88, %f210;
	mul.f32 	%f90, %f89, 0f377BA882;
	mad.f32 	%f93, %f90, %f207, %f227;
	mad.f32 	%f96, %f90, %f208, %f228;
	mad.f32 	%f99, %f90, %f209, %f229;
	add.f32 	%f101, %f230, %f210;
	mov.f32 	%f227, %f93;
	mov.f32 	%f228, %f96;
	mov.f32 	%f229, %f99;
	mov.f32 	%f230, %f101;
	mad.f32 	%f217, %f89, 0f377BA882, %f217;
	add.f32 	%f218, %f218, 0f3F800000;
	add.s32 	%r17, %r16, %r95;
	ld.param.u32 	%r92, [RadialBlur_param_8];
	setp.lt.u32 	%p20, %r17, %r92;
	mov.u32 	%r96, %r17;
	@%p20 bra 	BB9_12;
	bra.uni 	BB9_14;

BB9_13:
	mov.f32 	%f218, 0f00000000;
	mov.f32 	%f217, %f218;

BB9_14:
	setp.lt.f32 	%p21, %f217, 0f00000000;
	selp.f32 	%f26, 0fBF800000, 0f3F800000, %p21;
	mul.f32 	%f104, %f26, %f217;
	setp.ltu.f32 	%p22, %f104, 0f00000000;
	@%p22 bra 	BB9_16;

	rcp.approx.f32 	%f219, %f217;
	bra.uni 	BB9_17;

BB9_16:
	mul.f32 	%f219, %f26, 0f7F800000;

BB9_17:
	setp.lt.f32 	%p23, %f218, 0f00000000;
	selp.f32 	%f30, 0fBF800000, 0f3F800000, %p23;
	mul.f32 	%f105, %f30, %f218;
	setp.ltu.f32 	%p24, %f105, 0f00000000;
	@%p24 bra 	BB9_19;

	rcp.approx.f32 	%f220, %f218;
	bra.uni 	BB9_20;

BB9_19:
	mul.f32 	%f220, %f30, 0f7F800000;

BB9_20:
	mul.f32 	%f107, %f219, %f227;
	mul.f32 	%f109, %f219, %f228;
	mul.f32 	%f111, %f219, %f229;
	mul.f32 	%f113, %f220, %f230;
	mov.f32 	%f223, %f107;
	mov.f32 	%f224, %f109;
	mov.f32 	%f225, %f111;
	mov.f32 	%f226, %f113;
	bra.uni 	BB9_29;

BB9_21:
	@%p1 bra 	BB9_24;

	add.s32 	%r18, %r10, -1;
	add.s32 	%r19, %r11, -1;
	mov.f32 	%f221, 0f00000000;
	mov.u32 	%r60, 0;
	mov.u32 	%r97, %r60;

BB9_23:
	mov.u32 	%r20, %r97;
	shl.b32 	%r73, %r20, 2;
	ld.param.u32 	%r87, [RadialBlur_param_6];
	add.s32 	%r74, %r87, %r73;
	ld.const.f32 	%f115, [%r74];
	mad.f32 	%f116, %f42, %f115, %f211;
	ld.param.u32 	%r89, [RadialBlur_param_7];
	add.s32 	%r75, %r89, %r73;
	ld.const.f32 	%f117, [%r75];
	mul.f32 	%f118, %f44, %f117;
	sub.f32 	%f119, %f116, %f118;
	add.f32 	%f120, %f119, 0f3F000000;
	cvt.rzi.s32.f32 	%r62, %f120;
	// inline asm
	max.s32 	%r61, %r62, %r60;
	// inline asm
	// inline asm
	min.s32 	%r64, %r61, %r18;
	// inline asm
	mad.f32 	%f121, %f42, %f117, %f212;
	mad.f32 	%f122, %f44, %f115, %f121;
	add.f32 	%f123, %f122, 0f3F000000;
	cvt.rzi.s32.f32 	%r68, %f123;
	// inline asm
	max.s32 	%r67, %r68, %r60;
	// inline asm
	// inline asm
	min.s32 	%r70, %r67, %r19;
	// inline asm
	mad.lo.s32 	%r76, %r70, %r10, %r64;
	shl.b32 	%r77, %r76, 4;
	ld.param.u32 	%r82, [RadialBlur_param_0];
	add.s32 	%r78, %r82, %r77;
	ld.global.v4.f32 	{%f191, %f192, %f193, %f194}, [%r78];
	add.f32 	%f227, %f227, %f191;
	add.f32 	%f228, %f228, %f192;
	add.f32 	%f229, %f229, %f193;
	add.f32 	%f230, %f230, %f194;
	add.f32 	%f221, %f221, 0f3F800000;
	add.s32 	%r21, %r20, %r95;
	ld.param.u32 	%r91, [RadialBlur_param_8];
	setp.lt.u32 	%p25, %r21, %r91;
	mov.u32 	%r97, %r21;
	@%p25 bra 	BB9_23;
	bra.uni 	BB9_25;

BB9_24:
	mov.f32 	%f221, 0f00000000;

BB9_25:
	setp.lt.f32 	%p26, %f221, 0f00000000;
	selp.f32 	%f37, 0fBF800000, 0f3F800000, %p26;
	mul.f32 	%f125, %f37, %f221;
	setp.ltu.f32 	%p27, %f125, 0f00000000;
	@%p27 bra 	BB9_27;

	rcp.approx.f32 	%f222, %f221;
	bra.uni 	BB9_28;

BB9_27:
	mul.f32 	%f222, %f37, 0f7F800000;

BB9_28:
	mul.f32 	%f223, %f227, %f222;
	mul.f32 	%f224, %f228, %f222;
	mul.f32 	%f225, %f229, %f222;
	mul.f32 	%f226, %f230, %f222;

BB9_29:
	mov.f32 	%f130, 0f00000000;
	max.f32 	%f131, %f223, %f130;
	mov.f32 	%f132, 0f477FFF00;
	min.f32 	%f133, %f131, %f132;
	add.f32 	%f134, %f133, 0f3F000000;
	max.f32 	%f136, %f224, %f130;
	min.f32 	%f137, %f136, %f132;
	add.f32 	%f138, %f137, 0f3F000000;
	max.f32 	%f140, %f225, %f130;
	min.f32 	%f141, %f140, %f132;
	add.f32 	%f142, %f141, 0f3F000000;
	max.f32 	%f144, %f226, %f130;
	min.f32 	%f145, %f144, %f132;
	add.f32 	%f146, %f145, 0f3F000000;
	mad.lo.s32 	%r79, %r10, %r9, %r8;
	shl.b32 	%r80, %r79, 4;
	ld.param.u32 	%r84, [RadialBlur_param_1];
	add.s32 	%r81, %r84, %r80;
	st.global.v4.f32 	[%r81], {%f134, %f138, %f142, %f146};
	ret;
}

.entry Contrast(
	.param .u32 .ptr .global .align 16 Contrast_param_0,
	.param .u32 Contrast_param_1
)
{
	.reg .f32 	%f<184>;
	.reg .pred 	%p<26>;
	.reg .s32 	%r<29>;


	ld.param.u32 	%r14, [Contrast_param_0];
	ld.param.u32 	%r15, [Contrast_param_1];
	setp.eq.s32 	%p2, %r15, 0;
	selp.f32 	%f1, 0fBF800000, 0f3F800000, %p2;
	// inline asm
	mov.u32 	%r4, %envreg3;
	// inline asm
	// inline asm
	mov.u32 	%r5, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r6, %ctaid.x;
	// inline asm
	// inline asm
	mov.u32 	%r7, %tid.x;
	// inline asm
	// inline asm
	mov.u32 	%r8, %envreg4;
	// inline asm
	// inline asm
	mov.u32 	%r9, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r10, %ctaid.y;
	// inline asm
	// inline asm
	mov.u32 	%r11, %tid.y;
	// inline asm
	add.s32 	%r16, %r11, %r8;
	mad.lo.s32 	%r17, %r10, %r9, %r16;
	// inline asm
	mov.u32 	%r12, %envreg6;
	// inline asm
	// inline asm
	mov.u32 	%r13, %ntid.x;
	// inline asm
	mul.lo.s32 	%r18, %r17, %r12;
	mad.lo.s32 	%r19, %r6, %r5, %r4;
	add.s32 	%r20, %r19, %r7;
	mad.lo.s32 	%r21, %r18, %r13, %r20;
	shl.b32 	%r22, %r21, 4;
	add.s32 	%r1, %r14, %r22;
	ld.global.v4.f32 	{%f140, %f141, %f142, %f143}, [%r1];
	min.f32 	%f37, %f140, %f141;
	min.f32 	%f5, %f37, %f142;
	max.f32 	%f38, %f140, %f141;
	max.f32 	%f6, %f38, %f142;
	setp.neu.f32 	%p3, %f6, 0f00000000;
	@%p3 bra 	BB10_2;

	mov.f32 	%f39, 0f00000000;
	mov.f32 	%f181, %f39;
	mov.f32 	%f182, %f39;
	mov.f32 	%f183, %f39;
	mov.f32 	%f159, %f40;
	bra.uni 	BB10_9;

BB10_2:
	sub.f32 	%f7, %f6, %f5;
	div.full.f32 	%f41, %f7, %f6;
	mov.f32 	%f168, 0f00000000;
	mul.f32 	%f43, %f6, 0f377BA882;
	mov.f32 	%f181, %f168;
	mov.f32 	%f182, %f41;
	mov.f32 	%f183, %f43;
	mov.f32 	%f163, %f44;
	setp.neu.f32 	%p4, %f7, 0f00000000;
	@%p4 bra 	BB10_3;
	bra.uni 	BB10_9;

BB10_3:
	setp.eq.f32 	%p1, %f140, %f6;
	@%p1 bra 	BB10_5;

	setp.eq.f32 	%p5, %f141, %f6;
	selp.f32 	%f168, 0f40000000, 0f40800000, %p5;

BB10_5:
	@%p1 bra 	BB10_7;

	setp.eq.f32 	%p6, %f141, %f6;
	sub.f32 	%f46, %f140, %f141;
	sub.f32 	%f47, %f142, %f140;
	selp.f32 	%f169, %f47, %f46, %p6;
	bra.uni 	BB10_8;

BB10_7:
	sub.f32 	%f169, %f141, %f142;

BB10_8:
	div.full.f32 	%f48, %f169, %f7;
	add.f32 	%f49, %f168, %f48;
	div.full.f32 	%f50, %f49, 0f40C00000;
	setp.lt.f32 	%p7, %f50, 0f00000000;
	selp.f32 	%f51, 0f00000000, 0f3F800000, %p7;
	add.f32 	%f52, %f50, %f51;
	mov.f32 	%f181, %f52;
	mov.f32 	%f182, %f41;
	mov.f32 	%f183, %f43;
	mov.f32 	%f167, %f44;

BB10_9:
	mul.f32 	%f13, %f1, 0f3F000000;
	add.f32 	%f15, %f183, 0fBF000000;
	setp.eq.f32 	%p8, %f15, 0f7F800000;
	@%p8 bra 	BB10_15;

	setp.eq.f32 	%p9, %f15, 0fFF800000;
	setp.eq.f32 	%p10, %f15, 0f00000000;
	or.pred  	%p11, %p9, %p10;
	@%p11 bra 	BB10_15;

	mov.f32 	%f57, 0f40000000;
	mul.rn.f32 	%f54, %f57, %f15;
	// inline asm
	cvt.rni.f32.f32 	%f53, %f54;
	// inline asm
	cvt.rzi.s32.f32 	%r23, %f53;
	neg.f32 	%f58, %f53;
	mov.f32 	%f59, 0f3F000000;
	mul.rn.f32 	%f60, %f58, %f59;
	add.f32 	%f61, %f60, %f15;
	mov.f32 	%f62, 0f40490FDB;
	mul.rn.f32 	%f63, %f61, %f62;
	// inline asm
	abs.f32 	%f55, %f15;
	// inline asm
	setp.gt.f32 	%p12, %f55, 0f4B800000;
	selp.f32 	%f16, 0f00000000, %f63, %p12;
	selp.b32 	%r2, 0, %r23, %p12;
	and.b32  	%r24, %r2, 1;
	setp.eq.s32 	%p13, %r24, 0;
	mul.rn.f32 	%f17, %f16, %f16;
	@%p13 bra 	BB10_13;

	mov.f32 	%f64, 0f37CCF5CE;
	mul.rn.f32 	%f65, %f64, %f17;
	add.f32 	%f66, %f65, 0fBAB6061A;
	mul.rn.f32 	%f67, %f66, %f17;
	add.f32 	%f68, %f67, 0f3D2AAAA5;
	mul.rn.f32 	%f69, %f68, %f17;
	add.f32 	%f70, %f69, 0fBF000000;
	mul.rn.f32 	%f71, %f70, %f17;
	add.f32 	%f170, %f71, 0f3F800000;
	bra.uni 	BB10_14;

BB10_13:
	mov.f32 	%f72, 0fB94CA1F9;
	mul.rn.f32 	%f73, %f72, %f17;
	add.f32 	%f74, %f73, 0f3C08839E;
	mul.rn.f32 	%f75, %f74, %f17;
	add.f32 	%f76, %f75, 0fBE2AAAA3;
	mul.rn.f32 	%f77, %f76, %f17;
	mul.rn.f32 	%f78, %f77, %f16;
	add.f32 	%f170, %f78, %f16;

BB10_14:
	and.b32  	%r25, %r2, 2;
	setp.eq.s32 	%p14, %r25, 0;
	neg.f32 	%f79, %f170;
	selp.f32 	%f171, %f170, %f79, %p14;
	bra.uni 	BB10_16;

BB10_15:
	mov.f32 	%f80, 0f00000000;
	mul.rn.f32 	%f171, %f15, %f80;

BB10_16:
	add.f32 	%f81, %f171, 0f3F800000;
	mov.f32 	%f82, 0f3F000000;
	neg.f32 	%f83, %f183;
	mad.f32 	%f84, %f81, %f82, %f83;
	mad.f32 	%f85, %f13, %f84, %f183;
	mov.f32 	%f86, 0f00000000;
	cvt.sat.f32.f32 	%f24, %f85; 
	setp.eq.f32 	%p15, %f182, 0f00000000;
	mul.f32 	%f87, %f24, 0f477FFF00;
	mov.f32 	%f88, 0f477FFF00;
	max.f32 	%f89, %f87, %f86;
	min.f32 	%f90, %f89, %f88;
	add.f32 	%f27, %f90, 0f3F000000;
	@%p15 bra 	BB10_35;

	// inline asm
	cvt.rmi.f32.f32 	%f91, %f181;
	// inline asm
	sub.f32 	%f95, %f181, %f91;
	mul.f32 	%f94, %f95, 0f40C00000;
	mov.f32 	%f96, 0f40C00000;
	// inline asm
	cvt.rmi.f32.f32 	%f93, %f94;
	// inline asm
	neg.f32 	%f97, %f93;
	mad.f32 	%f98, %f95, %f96, %f97;
	mov.f32 	%f99, 0f3F800000;
	sub.f32 	%f100, %f99, %f182;
	mul.f32 	%f101, %f24, %f100;
	mul.f32 	%f102, %f182, %f98;
	sub.f32 	%f103, %f99, %f102;
	mul.f32 	%f104, %f24, %f103;
	sub.f32 	%f105, %f99, %f98;
	mul.f32 	%f106, %f182, %f105;
	sub.f32 	%f107, %f99, %f106;
	mul.f32 	%f108, %f24, %f107;
	mul.f32 	%f109, %f108, 0f477FFF00;
	max.f32 	%f112, %f109, %f86;
	min.f32 	%f113, %f112, %f88;
	add.f32 	%f28, %f113, 0f3F000000;
	mul.f32 	%f114, %f101, 0f477FFF00;
	max.f32 	%f115, %f114, %f86;
	min.f32 	%f116, %f115, %f88;
	add.f32 	%f29, %f116, 0f3F000000;
	mul.f32 	%f117, %f104, 0f477FFF00;
	max.f32 	%f118, %f117, %f86;
	min.f32 	%f119, %f118, %f88;
	add.f32 	%f30, %f119, 0f3F000000;
	cvt.rzi.s32.f32 	%r3, %f94;
	setp.eq.s32 	%p16, %r3, 1;
	@%p16 bra 	BB10_21;

	add.s32 	%r26, %r3, -2;
	setp.gt.u32 	%p17, %r26, 1;
	@%p17 bra 	BB10_20;

	mov.f32 	%f177, %f29;
	bra.uni 	BB10_22;

BB10_20:
	setp.eq.s32 	%p18, %r3, 4;
	selp.f32 	%f177, %f28, %f27, %p18;
	bra.uni 	BB10_22;

BB10_21:
	mov.f32 	%f177, %f30;

BB10_22:
	add.s32 	%r27, %r3, -1;
	setp.gt.u32 	%p19, %r27, 1;
	@%p19 bra 	BB10_24;

	mov.f32 	%f174, %f27;
	mov.f32 	%f176, %f174;
	bra.uni 	BB10_29;

BB10_24:
	setp.eq.s32 	%p20, %r3, 3;
	@%p20 bra 	BB10_28;

	setp.eq.s32 	%p21, %r3, 4;
	@%p21 bra 	BB10_27;

	setp.eq.s32 	%p22, %r3, 5;
	selp.f32 	%f33, %f29, %f28, %p22;
	mov.f32 	%f176, %f33;
	bra.uni 	BB10_29;

BB10_27:
	mov.f32 	%f176, %f29;
	bra.uni 	BB10_29;

BB10_28:
	mov.f32 	%f176, %f30;

BB10_29:
	mov.f32 	%f34, %f176;
	setp.eq.s32 	%p23, %r3, 2;
	@%p23 bra 	BB10_33;

	add.s32 	%r28, %r3, -3;
	setp.gt.u32 	%p24, %r28, 1;
	@%p24 bra 	BB10_32;

	mov.f32 	%f175, %f27;
	bra.uni 	BB10_34;

BB10_32:
	setp.eq.s32 	%p25, %r3, 5;
	selp.f32 	%f175, %f30, %f29, %p25;
	bra.uni 	BB10_34;

BB10_33:
	mov.f32 	%f175, %f28;

BB10_34:
	mov.f32 	%f178, %f177;
	mov.f32 	%f179, %f34;
	mov.f32 	%f180, %f175;
	mov.f32 	%f131, %f122;
	bra.uni 	BB10_36;

BB10_35:
	mov.f32 	%f178, %f27;
	mov.f32 	%f179, %f27;
	mov.f32 	%f180, %f27;
	mov.f32 	%f135, %f123;

BB10_36:
	st.global.v4.f32 	[%r1], {%f178, %f179, %f180, %f143};
	ret;
}

.entry ResizeHorizontalFilter(
	.param .u32 .ptr .global .align 16 ResizeHorizontalFilter_param_0,
	.param .u32 ResizeHorizontalFilter_param_1,
	.param .u32 ResizeHorizontalFilter_param_2,
	.param .u32 ResizeHorizontalFilter_param_3,
	.param .f32 ResizeHorizontalFilter_param_4,
	.param .u32 .ptr .global .align 16 ResizeHorizontalFilter_param_5,
	.param .u32 ResizeHorizontalFilter_param_6,
	.param .u32 ResizeHorizontalFilter_param_7,
	.param .u32 ResizeHorizontalFilter_param_8,
	.param .u32 ResizeHorizontalFilter_param_9,
	.param .u32 .ptr .global .align 4 ResizeHorizontalFilter_param_10,
	.param .f32 ResizeHorizontalFilter_param_11,
	.param .f32 ResizeHorizontalFilter_param_12,
	.param .f32 ResizeHorizontalFilter_param_13,
	.param .f32 ResizeHorizontalFilter_param_14,
	.param .u32 .ptr .shared .align 16 ResizeHorizontalFilter_param_15,
	.param .u32 ResizeHorizontalFilter_param_16,
	.param .u32 ResizeHorizontalFilter_param_17,
	.param .u32 ResizeHorizontalFilter_param_18,
	.param .u32 .ptr .shared .align 16 ResizeHorizontalFilter_param_19,
	.param .u32 .ptr .shared .align 4 ResizeHorizontalFilter_param_20,
	.param .u32 .ptr .shared .align 4 ResizeHorizontalFilter_param_21
)
.reqntid 256, 1, 1
{
	.local .align 4 .b8 	__local_depot11[28];
	.reg .b32 	%SP;
	.reg .f32 	%f<1128>;
	.reg .pred 	%p<355>;
	.reg .s32 	%r<1846>;


	mov.u32 	%SP, __local_depot11;
	ld.param.f32 	%f1, [ResizeHorizontalFilter_param_4];
	ld.param.u32 	%r5, [ResizeHorizontalFilter_param_6];
	ld.param.f32 	%f232, [ResizeHorizontalFilter_param_12];
	ld.param.u32 	%r536, [ResizeHorizontalFilter_param_17];
	// inline asm
	mov.u32 	%r531, %envreg0;
	// inline asm
	// inline asm
	mov.u32 	%r532, %ctaid.x;
	// inline asm
	add.s32 	%r537, %r532, %r531;
	mul.lo.s32 	%r15, %r537, %r536;
	mad.lo.s32 	%r534, %r537, %r536, %r536;
	// inline asm
	min.u32 	%r533, %r534, %r5;
	// inline asm
	rcp.approx.f32 	%f233, %f1;
	mov.f32 	%f234, 0f3F800000;
	add.f32 	%f235, %f233, 0f00000000;
	max.f32 	%f5, %f235, %f234;
	mul.f32 	%f236, %f5, %f232;
	mov.f32 	%f237, 0f3F000000;
	max.f32 	%f6, %f236, %f237;
	setp.lt.f32 	%p6, %f5, 0f00000000;
	selp.f32 	%f7, 0fBF800000, 0f3F800000, %p6;
	mul.f32 	%f238, %f7, %f5;
	setp.ltu.f32 	%p7, %f238, 0f00000000;
	@%p7 bra 	BB11_2;

	rcp.approx.f32 	%f1050, %f5;
	bra.uni 	BB11_3;

BB11_2:
	mul.f32 	%f1050, %f7, 0f7F800000;

BB11_3:
	cvt.rn.f32.u32 	%f239, %r15;
	add.f32 	%f240, %f239, 0f3F000000;
	ld.param.f32 	%f1044, [ResizeHorizontalFilter_param_4];
	div.full.f32 	%f241, %f240, %f1044;
	add.f32 	%f242, %f241, 0f00000000;
	sub.f32 	%f243, %f242, %f6;
	add.f32 	%f244, %f243, 0f3F000000;
	cvt.rzi.s32.f32 	%r539, %f244;
	mov.u32 	%r540, 0;
	// inline asm
	max.s32 	%r538, %r539, %r540;
	// inline asm
	ld.param.u32 	%r1700, [ResizeHorizontalFilter_param_16];
	add.s32 	%r542, %r538, %r1700;
	ld.param.u32 	%r1644, [ResizeHorizontalFilter_param_1];
	// inline asm
	min.s32 	%r541, %r542, %r1644;
	// inline asm
	// inline asm
	mov.u32 	%r544, %envreg4;
	// inline asm
	// inline asm
	mov.u32 	%r545, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r546, %ctaid.y;
	// inline asm
	// inline asm
	mov.u32 	%r547, %tid.y;
	// inline asm
	add.s32 	%r550, %r547, %r544;
	mad.lo.s32 	%r18, %r546, %r545, %r550;
	mul.lo.s32 	%r19, %r18, %r1644;
	sub.s32 	%r20, %r541, %r538;
	// inline asm
	mov.u32 	%r548, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r549, %tid.x;
	// inline asm
	setp.ge.u32 	%p8, %r549, %r20;
	mov.u32 	%r1709, %r549;
	@%p8 bra 	BB11_6;

	add.s32 	%r23, %r19, %r538;

BB11_5:
	add.s32 	%r551, %r23, %r1709;
	shl.b32 	%r552, %r551, 4;
	ld.param.u32 	%r1643, [ResizeHorizontalFilter_param_0];
	add.s32 	%r553, %r1643, %r552;
	shl.b32 	%r554, %r1709, 4;
	ld.param.u32 	%r1699, [ResizeHorizontalFilter_param_15];
	add.s32 	%r555, %r1699, %r554;
	ld.global.v4.f32 	{%f1039, %f1040, %f1041, %f1042}, [%r553];
	st.shared.v4.f32 	[%r555], {%f1039, %f1040, %f1041, %f1042};
	add.s32 	%r1709, %r1709, %r548;
	setp.lt.u32 	%p9, %r1709, %r20;
	@%p9 bra 	BB11_5;

BB11_6:
	membar.gl;
	bar.sync 	0;
	ld.param.u32 	%r1701, [ResizeHorizontalFilter_param_18];
	add.s32 	%r556, %r1701, %r533;
	add.s32 	%r557, %r556, -1;
	sub.s32 	%r558, %r557, %r15;
	div.u32 	%r26, %r558, %r1701;
	setp.eq.s32 	%p10, %r26, 0;
	@%p10 bra 	BB11_401;

	ld.param.u32 	%r1651, [ResizeHorizontalFilter_param_6];
	mul.lo.s32 	%r27, %r18, %r1651;
	ld.param.u32 	%r1645, [ResizeHorizontalFilter_param_1];
	cvt.rn.f32.u32 	%f11, %r1645;
	ld.param.u32 	%r1688, [ResizeHorizontalFilter_param_9];
	setp.eq.s32 	%p11, %r1688, 0;
	mov.u32 	%r1710, 0;
	ld.param.f32 	%f1047, [ResizeHorizontalFilter_param_13];
	setp.lt.f32 	%p12, %f1047, 0f00000000;
	or.pred  	%p1, %p12, %p11;
	mov.f32 	%f12, 0f7F800000;
	mov.f32 	%f13, 0fFF800000;
	mov.f32 	%f14, 0f7FFFFFFF;

BB11_8:
	ld.param.u32 	%r1702, [ResizeHorizontalFilter_param_18];
	mad.lo.s32 	%r29, %r1710, %r1702, %r15;
	add.s32 	%r561, %r29, %r1702;
	// inline asm
	min.u32 	%r560, %r561, %r533;
	// inline asm
	sub.s32 	%r30, %r560, %r29;
	// inline asm
	mov.u32 	%r563, %tid.x;
	// inline asm
	// inline asm
	mov.u32 	%r564, %ntid.x;
	// inline asm
	div.u32 	%r32, %r564, %r30;
	// inline asm
	mov.u32 	%r565, %ntid.x;
	// inline asm
	div.u32 	%r566, %r565, %r30;
	div.u32 	%r567, %r563, %r566;
	setp.lt.u32 	%p13, %r567, %r30;
	selp.b32 	%r33, %r567, -1, %p13;
	setp.eq.s32 	%p2, %r33, -1;
	@%p2 bra 	BB11_372;

	add.s32 	%r568, %r33, %r29;
	cvt.rn.f32.s32 	%f245, %r568;
	add.f32 	%f246, %f245, 0f3F000000;
	ld.param.f32 	%f1043, [ResizeHorizontalFilter_param_4];
	div.full.f32 	%f247, %f246, %f1043;
	add.f32 	%f15, %f247, 0f00000000;
	mov.f32 	%f1110, 0f00000000;
	sub.f32 	%f249, %f15, %f6;
	add.f32 	%f250, %f249, 0f3F000000;
	max.f32 	%f251, %f250, %f1110;
	cvt.rzi.u32.f32 	%r34, %f251;
	add.f32 	%f252, %f15, %f6;
	add.f32 	%f253, %f252, 0f3F000000;
	min.f32 	%f254, %f253, %f11;
	cvt.rzi.u32.f32 	%r569, %f254;
	sub.s32 	%r35, %r569, %r34;
	div.u32 	%r570, %r35, %r32;
	mul.lo.s32 	%r571, %r570, %r32;
	setp.ne.s32 	%p14, %r571, %r35;
	selp.u32 	%r572, 1, 0, %p14;
	add.s32 	%r36, %r572, %r570;
	rem.u32 	%r573, %r563, %r32;
	mul.lo.s32 	%r1777, %r36, %r573;
	setp.ge.u32 	%p15, %r1777, %r35;
	@%p15 bra 	BB11_372;

	add.s32 	%r575, %r1777, %r36;
	// inline asm
	min.u32 	%r574, %r575, %r35;
	// inline asm
	sub.s32 	%r577, %r34, %r538;
	add.s32 	%r1778, %r577, %r1777;
	setp.lt.u32 	%p3, %r1777, %r574;
	add.u32 	%r40, %SP, 0;
	ld.param.u32 	%r1649, [ResizeHorizontalFilter_param_3];
	setp.eq.s32 	%p16, %r1649, 0;
	@%p16 bra 	BB11_191;

	@!%p3 bra 	BB11_372;

	mov.f32 	%f1124, %f1110;
	mov.f32 	%f1125, %f1110;
	mov.f32 	%f1126, %f1110;
	mov.f32 	%f1127, %f1110;
	mov.f32 	%f1111, %f1110;

BB11_13:
	shl.b32 	%r578, %r1778, 4;
	ld.param.u32 	%r1698, [ResizeHorizontalFilter_param_15];
	add.s32 	%r579, %r1698, %r578;
	ld.shared.v4.f32 	{%f1027, %f1028, %f1029, %f1030}, [%r579];
	add.s32 	%r580, %r1777, %r34;
	cvt.rn.f32.u32 	%f259, %r580;
	sub.f32 	%f260, %f259, %f15;
	add.f32 	%f261, %f260, 0f3F000000;
	mul.f32 	%f262, %f1050, %f261;
	ld.param.f32 	%f1049, [ResizeHorizontalFilter_param_14];
	div.full.f32 	%f258, %f262, %f1049;
	// inline asm
	abs.f32 	%f257, %f258;
	// inline asm
	@%p1 bra 	BB11_101;

	ld.param.f32 	%f1045, [ResizeHorizontalFilter_param_11];
	mul.f32 	%f19, %f257, %f1045;
	ld.param.u32 	%r1687, [ResizeHorizontalFilter_param_9];
	setp.gt.s32 	%p17, %r1687, 2;
	@%p17 bra 	BB11_21;

	ld.param.u32 	%r1681, [ResizeHorizontalFilter_param_9];
	setp.eq.s32 	%p23, %r1681, 0;
	@%p23 bra 	BB11_101;

	ld.param.u32 	%r1680, [ResizeHorizontalFilter_param_9];
	setp.eq.s32 	%p24, %r1680, 1;
	@%p24 bra 	BB11_89;

	ld.param.u32 	%r1679, [ResizeHorizontalFilter_param_9];
	setp.eq.s32 	%p25, %r1679, 2;
	@%p25 bra 	BB11_18;
	bra.uni 	BB11_100;

BB11_18:
	setp.lt.f32 	%p87, %f19, 0f3F800000;
	@%p87 bra 	BB11_90;

	setp.geu.f32 	%p88, %f19, 0f40000000;
	@%p88 bra 	BB11_100;

	ld.param.u32 	%r1696, [ResizeHorizontalFilter_param_10];
	ld.global.f32 	%f365, [%r1696+24];
	ld.global.f32 	%f366, [%r1696+20];
	mad.f32 	%f367, %f19, %f365, %f366;
	ld.global.f32 	%f368, [%r1696+16];
	mad.f32 	%f369, %f19, %f367, %f368;
	ld.global.f32 	%f370, [%r1696+12];
	mad.f32 	%f1059, %f19, %f369, %f370;
	bra.uni 	BB11_102;

BB11_21:
	ld.param.u32 	%r1686, [ResizeHorizontalFilter_param_9];
	setp.gt.s32 	%p18, %r1686, 4;
	@%p18 bra 	BB11_27;

	ld.param.u32 	%r1683, [ResizeHorizontalFilter_param_9];
	setp.eq.s32 	%p21, %r1683, 3;
	@%p21 bra 	BB11_68;

	ld.param.u32 	%r1682, [ResizeHorizontalFilter_param_9];
	setp.eq.s32 	%p22, %r1682, 4;
	@%p22 bra 	BB11_24;
	bra.uni 	BB11_100;

BB11_24:
	mul.f32 	%f31, %f19, 0f40490FDC;
	setp.eq.f32 	%p46, %f31, %f12;
	setp.eq.f32 	%p47, %f31, %f13;
	or.pred  	%p48, %p46, %p47;
	@%p48 bra 	BB11_66;

	// inline asm
	abs.f32 	%f297, %f31;
	// inline asm
	setp.gt.f32 	%p49, %f297, 0f473BA700;
	@%p49 bra 	BB11_50;

	mov.f32 	%f301, 0f3F22F983;
	mul.rn.f32 	%f300, %f31, %f301;
	// inline asm
	cvt.rni.f32.f32 	%f299, %f300;
	// inline asm
	cvt.rzi.s32.f32 	%r1732, %f299;
	cvt.rn.f32.s32 	%f302, %r1732;
	mov.f32 	%f303, 0f3FC90000;
	mul.rn.f32 	%f304, %f302, %f303;
	sub.f32 	%f305, %f31, %f304;
	mov.f32 	%f306, 0f39FD8000;
	mul.rn.f32 	%f307, %f302, %f306;
	sub.f32 	%f308, %f305, %f307;
	mov.f32 	%f309, 0f34A88000;
	mul.rn.f32 	%f310, %f302, %f309;
	sub.f32 	%f311, %f308, %f310;
	mov.f32 	%f312, 0f2E85A309;
	mul.rn.f32 	%f313, %f302, %f312;
	sub.f32 	%f1053, %f311, %f313;
	bra.uni 	BB11_62;

BB11_27:
	ld.param.u32 	%r1685, [ResizeHorizontalFilter_param_9];
	add.s32 	%r581, %r1685, -9;
	setp.lt.u32 	%p19, %r581, 2;
	@%p19 bra 	BB11_91;

	ld.param.u32 	%r1684, [ResizeHorizontalFilter_param_9];
	setp.ne.s32 	%p20, %r1684, 5;
	@%p20 bra 	BB11_100;

	mul.f32 	%f20, %f19, 0f40490FDC;
	setp.eq.f32 	%p26, %f20, %f12;
	setp.eq.f32 	%p27, %f20, %f13;
	or.pred  	%p28, %p26, %p27;
	@%p28 bra 	BB11_48;

	// inline asm
	abs.f32 	%f263, %f20;
	// inline asm
	setp.gt.f32 	%p29, %f263, 0f473BA700;
	@%p29 bra 	BB11_32;

	mov.f32 	%f267, 0f3F22F983;
	mul.rn.f32 	%f266, %f20, %f267;
	// inline asm
	cvt.rni.f32.f32 	%f265, %f266;
	// inline asm
	cvt.rzi.s32.f32 	%r1721, %f265;
	cvt.rn.f32.s32 	%f268, %r1721;
	mov.f32 	%f269, 0f3FC90000;
	mul.rn.f32 	%f270, %f268, %f269;
	sub.f32 	%f271, %f20, %f270;
	mov.f32 	%f272, 0f39FD8000;
	mul.rn.f32 	%f273, %f268, %f272;
	sub.f32 	%f274, %f271, %f273;
	mov.f32 	%f275, 0f34A88000;
	mul.rn.f32 	%f276, %f268, %f275;
	sub.f32 	%f277, %f274, %f276;
	mov.f32 	%f278, 0f2E85A309;
	mul.rn.f32 	%f279, %f268, %f278;
	sub.f32 	%f1051, %f277, %f279;
	bra.uni 	BB11_44;

BB11_32:
	mov.b32 	 %r44, %f20;
	and.b32  	%r1713, %r44, -2147483648;
	shr.u32 	%r46, %r44, 23;
	and.b32  	%r600, %r46, 255;
	add.s32 	%r601, %r600, -128;
	shl.b32 	%r602, %r44, 8;
	or.b32  	%r599, %r602, -2147483648;
	shr.u32 	%r603, %r601, 5;
	mov.u32 	%r604, 4;
	sub.s32 	%r605, %r604, %r603;
	ld.const.u32 	%r583, [__GPU_i2opi_f];
	mul.lo.s32 	%r606, %r583, %r599;
	// inline asm
	mul.hi.u32 	%r582, %r583, %r599;
	// inline asm
	st.local.u32 	[%r40], %r606;
	ld.const.u32 	%r586, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r607, %r586, %r599;
	// inline asm
	mul.hi.u32 	%r585, %r586, %r599;
	// inline asm
	mad.lo.s32 	%r608, %r586, %r599, %r582;
	setp.lt.u32 	%p30, %r608, %r607;
	selp.u32 	%r609, 1, 0, %p30;
	add.s32 	%r610, %r609, %r585;
	st.local.u32 	[%r40+4], %r608;
	ld.const.u32 	%r589, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r611, %r589, %r599;
	// inline asm
	mul.hi.u32 	%r588, %r589, %r599;
	// inline asm
	mad.lo.s32 	%r612, %r589, %r599, %r610;
	setp.lt.u32 	%p31, %r612, %r611;
	selp.u32 	%r613, 1, 0, %p31;
	add.s32 	%r614, %r613, %r588;
	st.local.u32 	[%r40+8], %r612;
	ld.const.u32 	%r592, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r615, %r592, %r599;
	// inline asm
	mul.hi.u32 	%r591, %r592, %r599;
	// inline asm
	mad.lo.s32 	%r616, %r592, %r599, %r614;
	setp.lt.u32 	%p32, %r616, %r615;
	selp.u32 	%r617, 1, 0, %p32;
	add.s32 	%r618, %r617, %r591;
	st.local.u32 	[%r40+12], %r616;
	ld.const.u32 	%r595, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r619, %r595, %r599;
	// inline asm
	mul.hi.u32 	%r594, %r595, %r599;
	// inline asm
	mad.lo.s32 	%r620, %r595, %r599, %r618;
	setp.lt.u32 	%p33, %r620, %r619;
	selp.u32 	%r621, 1, 0, %p33;
	add.s32 	%r622, %r621, %r594;
	st.local.u32 	[%r40+16], %r620;
	ld.const.u32 	%r598, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r623, %r598, %r599;
	// inline asm
	mul.hi.u32 	%r597, %r598, %r599;
	// inline asm
	mad.lo.s32 	%r624, %r598, %r599, %r622;
	setp.lt.u32 	%p34, %r624, %r623;
	selp.u32 	%r625, 1, 0, %p34;
	add.s32 	%r626, %r625, %r597;
	st.local.u32 	[%r40+20], %r624;
	st.local.u32 	[%r40+24], %r626;
	and.b32  	%r47, %r46, 31;
	shl.b32 	%r628, %r605, 2;
	add.s32 	%r629, %r628, %r40;
	add.s32 	%r48, %r629, -16;
	ld.local.u32 	%r1711, [%r629+8];
	ld.local.u32 	%r1712, [%r629+4];
	setp.eq.s32 	%p35, %r47, 0;
	@%p35 bra 	BB11_34;

	shl.b32 	%r630, %r1711, %r47;
	neg.s32 	%r631, %r46;
	and.b32  	%r632, %r631, 31;
	shr.u32 	%r633, %r1712, %r632;
	or.b32  	%r1711, %r633, %r630;
	ld.local.u32 	%r634, [%r48+16];
	shr.u32 	%r635, %r634, %r632;
	shl.b32 	%r636, %r1712, %r47;
	or.b32  	%r1712, %r635, %r636;

BB11_34:
	shr.u32 	%r637, %r1712, 30;
	shl.b32 	%r638, %r1711, 2;
	or.b32  	%r1717, %r637, %r638;
	shl.b32 	%r56, %r1712, 2;
	setp.ne.s32 	%p36, %r56, 0;
	selp.u32 	%r639, 1, 0, %p36;
	add.s32 	%r640, %r639, %r1717;
	setp.gt.u32 	%p37, %r640, -2147483648;
	selp.u32 	%r641, 1, 0, %p37;
	shr.u32 	%r642, %r1711, 30;
	add.s32 	%r643, %r641, %r642;
	neg.s32 	%r644, %r643;
	setp.lt.s32 	%p38, %r44, 0;
	selp.b32 	%r1721, %r644, %r643, %p38;
	@%p37 bra 	BB11_36;

	mov.u32 	%r1716, %r56;
	bra.uni 	BB11_37;

BB11_36:
	not.b32 	%r645, %r1717;
	neg.s32 	%r58, %r56;
	setp.eq.s32 	%p39, %r56, 0;
	selp.u32 	%r646, 1, 0, %p39;
	add.s32 	%r1717, %r646, %r645;
	xor.b32  	%r1713, %r1713, -2147483648;
	mov.u32 	%r1716, %r58;

BB11_37:
	mov.u32 	%r1715, %r1716;
	setp.gt.s32 	%p40, %r1717, 0;
	@%p40 bra 	BB11_39;

	mov.u32 	%r1720, 0;
	bra.uni 	BB11_41;

BB11_39:
	mov.u32 	%r1720, 0;

BB11_40:
	shr.u32 	%r649, %r1715, 31;
	shl.b32 	%r650, %r1717, 1;
	or.b32  	%r1717, %r649, %r650;
	shl.b32 	%r1715, %r1715, 1;
	add.s32 	%r1720, %r1720, -1;
	setp.gt.s32 	%p41, %r1717, 0;
	@%p41 bra 	BB11_40;

BB11_41:
	mul.lo.s32 	%r1719, %r1717, -921707870;
	mov.u32 	%r653, -921707870;
	// inline asm
	mul.hi.u32 	%r651, %r1717, %r653;
	// inline asm
	setp.gt.s32 	%p42, %r651, 0;
	mov.u32 	%r1718, %r651;
	@%p42 bra 	BB11_42;
	bra.uni 	BB11_43;

BB11_42:
	shl.b32 	%r654, %r651, 1;
	shr.u32 	%r655, %r1719, 31;
	or.b32  	%r1718, %r654, %r655;
	mul.lo.s32 	%r1719, %r1717, -1843415740;
	add.s32 	%r1720, %r1720, -1;

BB11_43:
	setp.ne.s32 	%p43, %r1719, 0;
	selp.u32 	%r656, 1, 0, %p43;
	add.s32 	%r657, %r656, %r1718;
	shr.u32 	%r658, %r657, 8;
	shr.u32 	%r659, %r657, 7;
	and.b32  	%r660, %r659, 1;
	shl.b32 	%r661, %r1720, 23;
	add.s32 	%r662, %r661, %r658;
	add.s32 	%r663, %r662, %r660;
	add.s32 	%r664, %r663, 1056964608;
	or.b32  	%r665, %r664, %r1713;
	mov.b32 	 %f1051, %r665;

BB11_44:
	add.s32 	%r81, %r1721, 1;
	and.b32  	%r666, %r81, 1;
	setp.eq.s32 	%p44, %r666, 0;
	mul.rn.f32 	%f24, %f1051, %f1051;
	@%p44 bra 	BB11_46;

	mov.f32 	%f280, 0f37CCF5CE;
	mul.rn.f32 	%f281, %f280, %f24;
	add.f32 	%f282, %f281, 0fBAB6061A;
	mul.rn.f32 	%f283, %f282, %f24;
	add.f32 	%f284, %f283, 0f3D2AAAA5;
	mul.rn.f32 	%f285, %f284, %f24;
	add.f32 	%f286, %f285, 0fBF000000;
	mul.rn.f32 	%f287, %f286, %f24;
	add.f32 	%f1052, %f287, 0f3F800000;
	bra.uni 	BB11_47;

BB11_46:
	mov.f32 	%f288, 0fB94CA1F9;
	mul.rn.f32 	%f289, %f288, %f24;
	add.f32 	%f290, %f289, 0f3C08839E;
	mul.rn.f32 	%f291, %f290, %f24;
	add.f32 	%f292, %f291, 0fBE2AAAA3;
	mul.rn.f32 	%f293, %f292, %f24;
	mul.rn.f32 	%f294, %f293, %f1051;
	add.f32 	%f1052, %f294, %f1051;

BB11_47:
	and.b32  	%r667, %r81, 2;
	setp.eq.s32 	%p45, %r667, 0;
	neg.f32 	%f295, %f1052;
	selp.f32 	%f1106, %f1052, %f295, %p45;
	bra.uni 	BB11_49;

BB11_48:
	mov.f32 	%f1106, %f14;

BB11_49:
	mad.f32 	%f296, %f1106, 0f3E23D70A, 0f3F000000;
	mad.f32 	%f1059, %f1106, %f296, 0f3EAE147B;
	bra.uni 	BB11_102;

BB11_50:
	mov.b32 	 %r83, %f31;
	and.b32  	%r1724, %r83, -2147483648;
	shr.u32 	%r85, %r83, 23;
	and.b32  	%r686, %r85, 255;
	add.s32 	%r687, %r686, -128;
	shl.b32 	%r688, %r83, 8;
	or.b32  	%r685, %r688, -2147483648;
	shr.u32 	%r689, %r687, 5;
	mov.u32 	%r690, 4;
	sub.s32 	%r691, %r690, %r689;
	ld.const.u32 	%r669, [__GPU_i2opi_f];
	mul.lo.s32 	%r692, %r669, %r685;
	// inline asm
	mul.hi.u32 	%r668, %r669, %r685;
	// inline asm
	st.local.u32 	[%r40], %r692;
	ld.const.u32 	%r672, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r693, %r672, %r685;
	// inline asm
	mul.hi.u32 	%r671, %r672, %r685;
	// inline asm
	mad.lo.s32 	%r694, %r672, %r685, %r668;
	setp.lt.u32 	%p50, %r694, %r693;
	selp.u32 	%r695, 1, 0, %p50;
	add.s32 	%r696, %r695, %r671;
	st.local.u32 	[%r40+4], %r694;
	ld.const.u32 	%r675, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r697, %r675, %r685;
	// inline asm
	mul.hi.u32 	%r674, %r675, %r685;
	// inline asm
	mad.lo.s32 	%r698, %r675, %r685, %r696;
	setp.lt.u32 	%p51, %r698, %r697;
	selp.u32 	%r699, 1, 0, %p51;
	add.s32 	%r700, %r699, %r674;
	st.local.u32 	[%r40+8], %r698;
	ld.const.u32 	%r678, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r701, %r678, %r685;
	// inline asm
	mul.hi.u32 	%r677, %r678, %r685;
	// inline asm
	mad.lo.s32 	%r702, %r678, %r685, %r700;
	setp.lt.u32 	%p52, %r702, %r701;
	selp.u32 	%r703, 1, 0, %p52;
	add.s32 	%r704, %r703, %r677;
	st.local.u32 	[%r40+12], %r702;
	ld.const.u32 	%r681, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r705, %r681, %r685;
	// inline asm
	mul.hi.u32 	%r680, %r681, %r685;
	// inline asm
	mad.lo.s32 	%r706, %r681, %r685, %r704;
	setp.lt.u32 	%p53, %r706, %r705;
	selp.u32 	%r707, 1, 0, %p53;
	add.s32 	%r708, %r707, %r680;
	st.local.u32 	[%r40+16], %r706;
	ld.const.u32 	%r684, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r709, %r684, %r685;
	// inline asm
	mul.hi.u32 	%r683, %r684, %r685;
	// inline asm
	mad.lo.s32 	%r710, %r684, %r685, %r708;
	setp.lt.u32 	%p54, %r710, %r709;
	selp.u32 	%r711, 1, 0, %p54;
	add.s32 	%r712, %r711, %r683;
	st.local.u32 	[%r40+20], %r710;
	st.local.u32 	[%r40+24], %r712;
	and.b32  	%r86, %r85, 31;
	shl.b32 	%r714, %r691, 2;
	add.s32 	%r715, %r714, %r40;
	add.s32 	%r87, %r715, -16;
	ld.local.u32 	%r1722, [%r715+8];
	ld.local.u32 	%r1723, [%r715+4];
	setp.eq.s32 	%p55, %r86, 0;
	@%p55 bra 	BB11_52;

	shl.b32 	%r716, %r1722, %r86;
	neg.s32 	%r717, %r85;
	and.b32  	%r718, %r717, 31;
	shr.u32 	%r719, %r1723, %r718;
	or.b32  	%r1722, %r719, %r716;
	ld.local.u32 	%r720, [%r87+16];
	shr.u32 	%r721, %r720, %r718;
	shl.b32 	%r722, %r1723, %r86;
	or.b32  	%r1723, %r721, %r722;

BB11_52:
	shr.u32 	%r723, %r1723, 30;
	shl.b32 	%r724, %r1722, 2;
	or.b32  	%r1728, %r723, %r724;
	shl.b32 	%r95, %r1723, 2;
	setp.ne.s32 	%p56, %r95, 0;
	selp.u32 	%r725, 1, 0, %p56;
	add.s32 	%r726, %r725, %r1728;
	setp.gt.u32 	%p57, %r726, -2147483648;
	selp.u32 	%r727, 1, 0, %p57;
	shr.u32 	%r728, %r1722, 30;
	add.s32 	%r729, %r727, %r728;
	neg.s32 	%r730, %r729;
	setp.lt.s32 	%p58, %r83, 0;
	selp.b32 	%r1732, %r730, %r729, %p58;
	@%p57 bra 	BB11_54;

	mov.u32 	%r1727, %r95;
	bra.uni 	BB11_55;

BB11_54:
	not.b32 	%r731, %r1728;
	neg.s32 	%r97, %r95;
	setp.eq.s32 	%p59, %r95, 0;
	selp.u32 	%r732, 1, 0, %p59;
	add.s32 	%r1728, %r732, %r731;
	xor.b32  	%r1724, %r1724, -2147483648;
	mov.u32 	%r1727, %r97;

BB11_55:
	mov.u32 	%r1726, %r1727;
	setp.gt.s32 	%p60, %r1728, 0;
	@%p60 bra 	BB11_57;

	mov.u32 	%r1731, 0;
	bra.uni 	BB11_59;

BB11_57:
	mov.u32 	%r1731, 0;

BB11_58:
	shr.u32 	%r735, %r1726, 31;
	shl.b32 	%r736, %r1728, 1;
	or.b32  	%r1728, %r735, %r736;
	shl.b32 	%r1726, %r1726, 1;
	add.s32 	%r1731, %r1731, -1;
	setp.gt.s32 	%p61, %r1728, 0;
	@%p61 bra 	BB11_58;

BB11_59:
	mul.lo.s32 	%r1730, %r1728, -921707870;
	mov.u32 	%r739, -921707870;
	// inline asm
	mul.hi.u32 	%r737, %r1728, %r739;
	// inline asm
	setp.gt.s32 	%p62, %r737, 0;
	mov.u32 	%r1729, %r737;
	@%p62 bra 	BB11_60;
	bra.uni 	BB11_61;

BB11_60:
	shl.b32 	%r740, %r737, 1;
	shr.u32 	%r741, %r1730, 31;
	or.b32  	%r1729, %r740, %r741;
	mul.lo.s32 	%r1730, %r1728, -1843415740;
	add.s32 	%r1731, %r1731, -1;

BB11_61:
	setp.ne.s32 	%p63, %r1730, 0;
	selp.u32 	%r742, 1, 0, %p63;
	add.s32 	%r743, %r742, %r1729;
	shr.u32 	%r744, %r743, 8;
	shr.u32 	%r745, %r743, 7;
	and.b32  	%r746, %r745, 1;
	shl.b32 	%r747, %r1731, 23;
	add.s32 	%r748, %r747, %r744;
	add.s32 	%r749, %r748, %r746;
	add.s32 	%r750, %r749, 1056964608;
	or.b32  	%r751, %r750, %r1724;
	mov.b32 	 %f1053, %r751;

BB11_62:
	add.s32 	%r120, %r1732, 1;
	and.b32  	%r752, %r120, 1;
	setp.eq.s32 	%p64, %r752, 0;
	mul.rn.f32 	%f35, %f1053, %f1053;
	@%p64 bra 	BB11_64;

	mov.f32 	%f314, 0f37CCF5CE;
	mul.rn.f32 	%f315, %f314, %f35;
	add.f32 	%f316, %f315, 0fBAB6061A;
	mul.rn.f32 	%f317, %f316, %f35;
	add.f32 	%f318, %f317, 0f3D2AAAA5;
	mul.rn.f32 	%f319, %f318, %f35;
	add.f32 	%f320, %f319, 0fBF000000;
	mul.rn.f32 	%f321, %f320, %f35;
	add.f32 	%f1054, %f321, 0f3F800000;
	bra.uni 	BB11_65;

BB11_64:
	mov.f32 	%f322, 0fB94CA1F9;
	mul.rn.f32 	%f323, %f322, %f35;
	add.f32 	%f324, %f323, 0f3C08839E;
	mul.rn.f32 	%f325, %f324, %f35;
	add.f32 	%f326, %f325, 0fBE2AAAA3;
	mul.rn.f32 	%f327, %f326, %f35;
	mul.rn.f32 	%f328, %f327, %f1053;
	add.f32 	%f1054, %f328, %f1053;

BB11_65:
	and.b32  	%r753, %r120, 2;
	setp.eq.s32 	%p65, %r753, 0;
	neg.f32 	%f329, %f1054;
	selp.f32 	%f1105, %f1054, %f329, %p65;
	bra.uni 	BB11_67;

BB11_66:
	mov.f32 	%f1105, %f14;

BB11_67:
	mad.f32 	%f1059, %f1105, 0f3EEB851F, 0f3F0A3D71;
	bra.uni 	BB11_102;

BB11_68:
	mul.f32 	%f42, %f19, 0f40490FDC;
	setp.eq.f32 	%p66, %f42, %f12;
	setp.eq.f32 	%p67, %f42, %f13;
	or.pred  	%p68, %p66, %p67;
	@%p68 bra 	BB11_87;

	// inline asm
	abs.f32 	%f330, %f42;
	// inline asm
	setp.gt.f32 	%p69, %f330, 0f473BA700;
	@%p69 bra 	BB11_71;

	mov.f32 	%f334, 0f3F22F983;
	mul.rn.f32 	%f333, %f42, %f334;
	// inline asm
	cvt.rni.f32.f32 	%f332, %f333;
	// inline asm
	cvt.rzi.s32.f32 	%r1743, %f332;
	cvt.rn.f32.s32 	%f335, %r1743;
	mov.f32 	%f336, 0f3FC90000;
	mul.rn.f32 	%f337, %f335, %f336;
	sub.f32 	%f338, %f42, %f337;
	mov.f32 	%f339, 0f39FD8000;
	mul.rn.f32 	%f340, %f335, %f339;
	sub.f32 	%f341, %f338, %f340;
	mov.f32 	%f342, 0f34A88000;
	mul.rn.f32 	%f343, %f335, %f342;
	sub.f32 	%f344, %f341, %f343;
	mov.f32 	%f345, 0f2E85A309;
	mul.rn.f32 	%f346, %f335, %f345;
	sub.f32 	%f1055, %f344, %f346;
	bra.uni 	BB11_83;

BB11_71:
	mov.b32 	 %r122, %f42;
	and.b32  	%r1735, %r122, -2147483648;
	shr.u32 	%r124, %r122, 23;
	and.b32  	%r772, %r124, 255;
	add.s32 	%r773, %r772, -128;
	shl.b32 	%r774, %r122, 8;
	or.b32  	%r771, %r774, -2147483648;
	shr.u32 	%r775, %r773, 5;
	mov.u32 	%r776, 4;
	sub.s32 	%r777, %r776, %r775;
	ld.const.u32 	%r755, [__GPU_i2opi_f];
	mul.lo.s32 	%r778, %r755, %r771;
	// inline asm
	mul.hi.u32 	%r754, %r755, %r771;
	// inline asm
	st.local.u32 	[%r40], %r778;
	ld.const.u32 	%r758, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r779, %r758, %r771;
	// inline asm
	mul.hi.u32 	%r757, %r758, %r771;
	// inline asm
	mad.lo.s32 	%r780, %r758, %r771, %r754;
	setp.lt.u32 	%p70, %r780, %r779;
	selp.u32 	%r781, 1, 0, %p70;
	add.s32 	%r782, %r781, %r757;
	st.local.u32 	[%r40+4], %r780;
	ld.const.u32 	%r761, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r783, %r761, %r771;
	// inline asm
	mul.hi.u32 	%r760, %r761, %r771;
	// inline asm
	mad.lo.s32 	%r784, %r761, %r771, %r782;
	setp.lt.u32 	%p71, %r784, %r783;
	selp.u32 	%r785, 1, 0, %p71;
	add.s32 	%r786, %r785, %r760;
	st.local.u32 	[%r40+8], %r784;
	ld.const.u32 	%r764, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r787, %r764, %r771;
	// inline asm
	mul.hi.u32 	%r763, %r764, %r771;
	// inline asm
	mad.lo.s32 	%r788, %r764, %r771, %r786;
	setp.lt.u32 	%p72, %r788, %r787;
	selp.u32 	%r789, 1, 0, %p72;
	add.s32 	%r790, %r789, %r763;
	st.local.u32 	[%r40+12], %r788;
	ld.const.u32 	%r767, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r791, %r767, %r771;
	// inline asm
	mul.hi.u32 	%r766, %r767, %r771;
	// inline asm
	mad.lo.s32 	%r792, %r767, %r771, %r790;
	setp.lt.u32 	%p73, %r792, %r791;
	selp.u32 	%r793, 1, 0, %p73;
	add.s32 	%r794, %r793, %r766;
	st.local.u32 	[%r40+16], %r792;
	ld.const.u32 	%r770, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r795, %r770, %r771;
	// inline asm
	mul.hi.u32 	%r769, %r770, %r771;
	// inline asm
	mad.lo.s32 	%r796, %r770, %r771, %r794;
	setp.lt.u32 	%p74, %r796, %r795;
	selp.u32 	%r797, 1, 0, %p74;
	add.s32 	%r798, %r797, %r769;
	st.local.u32 	[%r40+20], %r796;
	st.local.u32 	[%r40+24], %r798;
	and.b32  	%r125, %r124, 31;
	shl.b32 	%r800, %r777, 2;
	add.s32 	%r801, %r800, %r40;
	add.s32 	%r126, %r801, -16;
	ld.local.u32 	%r1733, [%r801+8];
	ld.local.u32 	%r1734, [%r801+4];
	setp.eq.s32 	%p75, %r125, 0;
	@%p75 bra 	BB11_73;

	shl.b32 	%r802, %r1733, %r125;
	neg.s32 	%r803, %r124;
	and.b32  	%r804, %r803, 31;
	shr.u32 	%r805, %r1734, %r804;
	or.b32  	%r1733, %r805, %r802;
	ld.local.u32 	%r806, [%r126+16];
	shr.u32 	%r807, %r806, %r804;
	shl.b32 	%r808, %r1734, %r125;
	or.b32  	%r1734, %r807, %r808;

BB11_73:
	shr.u32 	%r809, %r1734, 30;
	shl.b32 	%r810, %r1733, 2;
	or.b32  	%r1739, %r809, %r810;
	shl.b32 	%r134, %r1734, 2;
	setp.ne.s32 	%p76, %r134, 0;
	selp.u32 	%r811, 1, 0, %p76;
	add.s32 	%r812, %r811, %r1739;
	setp.gt.u32 	%p77, %r812, -2147483648;
	selp.u32 	%r813, 1, 0, %p77;
	shr.u32 	%r814, %r1733, 30;
	add.s32 	%r815, %r813, %r814;
	neg.s32 	%r816, %r815;
	setp.lt.s32 	%p78, %r122, 0;
	selp.b32 	%r1743, %r816, %r815, %p78;
	@%p77 bra 	BB11_75;

	mov.u32 	%r1738, %r134;
	bra.uni 	BB11_76;

BB11_75:
	not.b32 	%r817, %r1739;
	neg.s32 	%r136, %r134;
	setp.eq.s32 	%p79, %r134, 0;
	selp.u32 	%r818, 1, 0, %p79;
	add.s32 	%r1739, %r818, %r817;
	xor.b32  	%r1735, %r1735, -2147483648;
	mov.u32 	%r1738, %r136;

BB11_76:
	mov.u32 	%r1737, %r1738;
	setp.gt.s32 	%p80, %r1739, 0;
	@%p80 bra 	BB11_78;

	mov.u32 	%r1742, 0;
	bra.uni 	BB11_80;

BB11_78:
	mov.u32 	%r1742, 0;

BB11_79:
	shr.u32 	%r821, %r1737, 31;
	shl.b32 	%r822, %r1739, 1;
	or.b32  	%r1739, %r821, %r822;
	shl.b32 	%r1737, %r1737, 1;
	add.s32 	%r1742, %r1742, -1;
	setp.gt.s32 	%p81, %r1739, 0;
	@%p81 bra 	BB11_79;

BB11_80:
	mul.lo.s32 	%r1741, %r1739, -921707870;
	mov.u32 	%r825, -921707870;
	// inline asm
	mul.hi.u32 	%r823, %r1739, %r825;
	// inline asm
	setp.gt.s32 	%p82, %r823, 0;
	mov.u32 	%r1740, %r823;
	@%p82 bra 	BB11_81;
	bra.uni 	BB11_82;

BB11_81:
	shl.b32 	%r826, %r823, 1;
	shr.u32 	%r827, %r1741, 31;
	or.b32  	%r1740, %r826, %r827;
	mul.lo.s32 	%r1741, %r1739, -1843415740;
	add.s32 	%r1742, %r1742, -1;

BB11_82:
	setp.ne.s32 	%p83, %r1741, 0;
	selp.u32 	%r828, 1, 0, %p83;
	add.s32 	%r829, %r828, %r1740;
	shr.u32 	%r830, %r829, 8;
	shr.u32 	%r831, %r829, 7;
	and.b32  	%r832, %r831, 1;
	shl.b32 	%r833, %r1742, 23;
	add.s32 	%r834, %r833, %r830;
	add.s32 	%r835, %r834, %r832;
	add.s32 	%r836, %r835, 1056964608;
	or.b32  	%r837, %r836, %r1735;
	mov.b32 	 %f1055, %r837;

BB11_83:
	add.s32 	%r159, %r1743, 1;
	and.b32  	%r838, %r159, 1;
	setp.eq.s32 	%p84, %r838, 0;
	mul.rn.f32 	%f46, %f1055, %f1055;
	@%p84 bra 	BB11_85;

	mov.f32 	%f347, 0f37CCF5CE;
	mul.rn.f32 	%f348, %f347, %f46;
	add.f32 	%f349, %f348, 0fBAB6061A;
	mul.rn.f32 	%f350, %f349, %f46;
	add.f32 	%f351, %f350, 0f3D2AAAA5;
	mul.rn.f32 	%f352, %f351, %f46;
	add.f32 	%f353, %f352, 0fBF000000;
	mul.rn.f32 	%f354, %f353, %f46;
	add.f32 	%f1056, %f354, 0f3F800000;
	bra.uni 	BB11_86;

BB11_85:
	mov.f32 	%f355, 0fB94CA1F9;
	mul.rn.f32 	%f356, %f355, %f46;
	add.f32 	%f357, %f356, 0f3C08839E;
	mul.rn.f32 	%f358, %f357, %f46;
	add.f32 	%f359, %f358, 0fBE2AAAA3;
	mul.rn.f32 	%f360, %f359, %f46;
	mul.rn.f32 	%f361, %f360, %f1055;
	add.f32 	%f1056, %f361, %f1055;

BB11_86:
	and.b32  	%r839, %r159, 2;
	setp.eq.s32 	%p85, %r839, 0;
	neg.f32 	%f362, %f1056;
	selp.f32 	%f1104, %f1056, %f362, %p85;
	bra.uni 	BB11_88;

BB11_87:
	mov.f32 	%f1104, %f14;

BB11_88:
	mad.f32 	%f1059, %f1104, 0f3F000000, 0f3F000000;
	bra.uni 	BB11_102;

BB11_89:
	setp.lt.f32 	%p86, %f19, 0f3F800000;
	sub.f32 	%f364, %f234, %f19;
	selp.f32 	%f1059, %f364, 0f00000000, %p86;
	bra.uni 	BB11_102;

BB11_90:
	ld.param.u32 	%r1695, [ResizeHorizontalFilter_param_10];
	ld.global.f32 	%f371, [%r1695];
	ld.global.f32 	%f372, [%r1695+8];
	ld.global.f32 	%f373, [%r1695+4];
	mad.f32 	%f374, %f19, %f372, %f373;
	mul.f32 	%f375, %f19, %f374;
	mad.f32 	%f1059, %f19, %f375, %f371;
	bra.uni 	BB11_102;

BB11_91:
	setp.eq.f32 	%p89, %f19, 0f00000000;
	@%p89 bra 	BB11_101;

	mul.f32 	%f56, %f19, 0f40490FDC;
	setp.eq.f32 	%p90, %f19, %f12;
	@%p90 bra 	BB11_98;

	setp.eq.f32 	%p91, %f19, %f13;
	or.pred  	%p93, %p91, %p89;
	@%p93 bra 	BB11_98;

	mov.f32 	%f380, 0f40000000;
	mul.rn.f32 	%f377, %f380, %f19;
	// inline asm
	cvt.rni.f32.f32 	%f376, %f377;
	// inline asm
	cvt.rzi.s32.f32 	%r840, %f376;
	neg.f32 	%f381, %f376;
	mul.rn.f32 	%f383, %f381, %f237;
	add.f32 	%f384, %f383, %f19;
	mov.f32 	%f385, 0f40490FDB;
	mul.rn.f32 	%f386, %f384, %f385;
	// inline asm
	abs.f32 	%f378, %f19;
	// inline asm
	setp.gt.f32 	%p94, %f378, 0f4B800000;
	selp.f32 	%f57, 0f00000000, %f386, %p94;
	selp.b32 	%r160, 0, %r840, %p94;
	and.b32  	%r841, %r160, 1;
	setp.eq.s32 	%p95, %r841, 0;
	mul.rn.f32 	%f58, %f57, %f57;
	@%p95 bra 	BB11_96;

	mov.f32 	%f387, 0f37CCF5CE;
	mul.rn.f32 	%f388, %f387, %f58;
	add.f32 	%f389, %f388, 0fBAB6061A;
	mul.rn.f32 	%f390, %f389, %f58;
	add.f32 	%f391, %f390, 0f3D2AAAA5;
	mul.rn.f32 	%f392, %f391, %f58;
	add.f32 	%f393, %f392, 0fBF000000;
	mul.rn.f32 	%f394, %f393, %f58;
	add.f32 	%f1057, %f394, 0f3F800000;
	bra.uni 	BB11_97;

BB11_96:
	mov.f32 	%f395, 0fB94CA1F9;
	mul.rn.f32 	%f396, %f395, %f58;
	add.f32 	%f397, %f396, 0f3C08839E;
	mul.rn.f32 	%f398, %f397, %f58;
	add.f32 	%f399, %f398, 0fBE2AAAA3;
	mul.rn.f32 	%f400, %f399, %f58;
	mul.rn.f32 	%f401, %f400, %f57;
	add.f32 	%f1057, %f401, %f57;

BB11_97:
	and.b32  	%r842, %r160, 2;
	setp.eq.s32 	%p96, %r842, 0;
	neg.f32 	%f402, %f1057;
	selp.f32 	%f1058, %f1057, %f402, %p96;
	bra.uni 	BB11_99;

BB11_98:
	mov.f32 	%f403, 0f00000000;
	mul.rn.f32 	%f1058, %f19, %f403;

BB11_99:
	div.full.f32 	%f1059, %f1058, %f56;
	bra.uni 	BB11_102;

BB11_100:
	mov.f32 	%f1059, 0f00000000;
	bra.uni 	BB11_102;

BB11_101:
	mov.f32 	%f1059, 0f3F800000;

BB11_102:
	ld.param.u32 	%r1669, [ResizeHorizontalFilter_param_8];
	setp.gt.s32 	%p97, %r1669, 2;
	@%p97 bra 	BB11_109;

	ld.param.u32 	%r1663, [ResizeHorizontalFilter_param_8];
	setp.eq.s32 	%p103, %r1663, 0;
	@%p103 bra 	BB11_180;

	ld.param.u32 	%r1662, [ResizeHorizontalFilter_param_8];
	setp.eq.s32 	%p104, %r1662, 1;
	@%p104 bra 	BB11_177;

	ld.param.u32 	%r1661, [ResizeHorizontalFilter_param_8];
	setp.eq.s32 	%p105, %r1661, 2;
	@%p105 bra 	BB11_106;
	bra.uni 	BB11_189;

BB11_106:
	setp.lt.f32 	%p167, %f257, 0f3F800000;
	@%p167 bra 	BB11_178;

	setp.geu.f32 	%p168, %f257, 0f40000000;
	@%p168 bra 	BB11_189;

	ld.param.u32 	%r1694, [ResizeHorizontalFilter_param_10];
	ld.global.f32 	%f508, [%r1694+24];
	ld.global.f32 	%f509, [%r1694+20];
	mad.f32 	%f510, %f257, %f508, %f509;
	ld.global.f32 	%f511, [%r1694+16];
	mad.f32 	%f512, %f257, %f510, %f511;
	ld.global.f32 	%f513, [%r1694+12];
	mad.f32 	%f101, %f257, %f512, %f513;
	mov.f32 	%f1068, %f101;
	bra.uni 	BB11_190;

BB11_109:
	ld.param.u32 	%r1668, [ResizeHorizontalFilter_param_8];
	setp.gt.s32 	%p98, %r1668, 4;
	@%p98 bra 	BB11_115;

	ld.param.u32 	%r1665, [ResizeHorizontalFilter_param_8];
	setp.eq.s32 	%p101, %r1665, 3;
	@%p101 bra 	BB11_156;

	ld.param.u32 	%r1664, [ResizeHorizontalFilter_param_8];
	setp.eq.s32 	%p102, %r1664, 4;
	@%p102 bra 	BB11_112;
	bra.uni 	BB11_189;

BB11_112:
	mul.f32 	%f78, %f257, 0f40490FDC;
	setp.eq.f32 	%p126, %f78, %f12;
	setp.eq.f32 	%p127, %f78, %f13;
	or.pred  	%p128, %p126, %p127;
	@%p128 bra 	BB11_154;

	// inline asm
	abs.f32 	%f440, %f78;
	// inline asm
	setp.gt.f32 	%p129, %f440, 0f473BA700;
	@%p129 bra 	BB11_138;

	mov.f32 	%f444, 0f3F22F983;
	mul.rn.f32 	%f443, %f78, %f444;
	// inline asm
	cvt.rni.f32.f32 	%f442, %f443;
	// inline asm
	cvt.rzi.s32.f32 	%r1765, %f442;
	cvt.rn.f32.s32 	%f445, %r1765;
	mov.f32 	%f446, 0f3FC90000;
	mul.rn.f32 	%f447, %f445, %f446;
	sub.f32 	%f448, %f78, %f447;
	mov.f32 	%f449, 0f39FD8000;
	mul.rn.f32 	%f450, %f445, %f449;
	sub.f32 	%f451, %f448, %f450;
	mov.f32 	%f452, 0f34A88000;
	mul.rn.f32 	%f453, %f445, %f452;
	sub.f32 	%f454, %f451, %f453;
	mov.f32 	%f455, 0f2E85A309;
	mul.rn.f32 	%f456, %f445, %f455;
	sub.f32 	%f1062, %f454, %f456;
	bra.uni 	BB11_150;

BB11_115:
	ld.param.u32 	%r1667, [ResizeHorizontalFilter_param_8];
	add.s32 	%r843, %r1667, -9;
	setp.lt.u32 	%p99, %r843, 2;
	@%p99 bra 	BB11_179;

	ld.param.u32 	%r1666, [ResizeHorizontalFilter_param_8];
	setp.ne.s32 	%p100, %r1666, 5;
	@%p100 bra 	BB11_189;

	mul.f32 	%f67, %f257, 0f40490FDC;
	setp.eq.f32 	%p106, %f67, %f12;
	setp.eq.f32 	%p107, %f67, %f13;
	or.pred  	%p108, %p106, %p107;
	@%p108 bra 	BB11_136;

	// inline asm
	abs.f32 	%f406, %f67;
	// inline asm
	setp.gt.f32 	%p109, %f406, 0f473BA700;
	@%p109 bra 	BB11_120;

	mov.f32 	%f410, 0f3F22F983;
	mul.rn.f32 	%f409, %f67, %f410;
	// inline asm
	cvt.rni.f32.f32 	%f408, %f409;
	// inline asm
	cvt.rzi.s32.f32 	%r1754, %f408;
	cvt.rn.f32.s32 	%f411, %r1754;
	mov.f32 	%f412, 0f3FC90000;
	mul.rn.f32 	%f413, %f411, %f412;
	sub.f32 	%f414, %f67, %f413;
	mov.f32 	%f415, 0f39FD8000;
	mul.rn.f32 	%f416, %f411, %f415;
	sub.f32 	%f417, %f414, %f416;
	mov.f32 	%f418, 0f34A88000;
	mul.rn.f32 	%f419, %f411, %f418;
	sub.f32 	%f420, %f417, %f419;
	mov.f32 	%f421, 0f2E85A309;
	mul.rn.f32 	%f422, %f411, %f421;
	sub.f32 	%f1060, %f420, %f422;
	bra.uni 	BB11_132;

BB11_120:
	mov.b32 	 %r162, %f67;
	and.b32  	%r1746, %r162, -2147483648;
	shr.u32 	%r164, %r162, 23;
	and.b32  	%r862, %r164, 255;
	add.s32 	%r863, %r862, -128;
	shl.b32 	%r864, %r162, 8;
	or.b32  	%r861, %r864, -2147483648;
	shr.u32 	%r865, %r863, 5;
	mov.u32 	%r866, 4;
	sub.s32 	%r867, %r866, %r865;
	ld.const.u32 	%r845, [__GPU_i2opi_f];
	mul.lo.s32 	%r868, %r845, %r861;
	// inline asm
	mul.hi.u32 	%r844, %r845, %r861;
	// inline asm
	st.local.u32 	[%r40], %r868;
	ld.const.u32 	%r848, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r869, %r848, %r861;
	// inline asm
	mul.hi.u32 	%r847, %r848, %r861;
	// inline asm
	mad.lo.s32 	%r870, %r848, %r861, %r844;
	setp.lt.u32 	%p110, %r870, %r869;
	selp.u32 	%r871, 1, 0, %p110;
	add.s32 	%r872, %r871, %r847;
	st.local.u32 	[%r40+4], %r870;
	ld.const.u32 	%r851, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r873, %r851, %r861;
	// inline asm
	mul.hi.u32 	%r850, %r851, %r861;
	// inline asm
	mad.lo.s32 	%r874, %r851, %r861, %r872;
	setp.lt.u32 	%p111, %r874, %r873;
	selp.u32 	%r875, 1, 0, %p111;
	add.s32 	%r876, %r875, %r850;
	st.local.u32 	[%r40+8], %r874;
	ld.const.u32 	%r854, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r877, %r854, %r861;
	// inline asm
	mul.hi.u32 	%r853, %r854, %r861;
	// inline asm
	mad.lo.s32 	%r878, %r854, %r861, %r876;
	setp.lt.u32 	%p112, %r878, %r877;
	selp.u32 	%r879, 1, 0, %p112;
	add.s32 	%r880, %r879, %r853;
	st.local.u32 	[%r40+12], %r878;
	ld.const.u32 	%r857, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r881, %r857, %r861;
	// inline asm
	mul.hi.u32 	%r856, %r857, %r861;
	// inline asm
	mad.lo.s32 	%r882, %r857, %r861, %r880;
	setp.lt.u32 	%p113, %r882, %r881;
	selp.u32 	%r883, 1, 0, %p113;
	add.s32 	%r884, %r883, %r856;
	st.local.u32 	[%r40+16], %r882;
	ld.const.u32 	%r860, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r885, %r860, %r861;
	// inline asm
	mul.hi.u32 	%r859, %r860, %r861;
	// inline asm
	mad.lo.s32 	%r886, %r860, %r861, %r884;
	setp.lt.u32 	%p114, %r886, %r885;
	selp.u32 	%r887, 1, 0, %p114;
	add.s32 	%r888, %r887, %r859;
	st.local.u32 	[%r40+20], %r886;
	st.local.u32 	[%r40+24], %r888;
	and.b32  	%r165, %r164, 31;
	shl.b32 	%r890, %r867, 2;
	add.s32 	%r891, %r890, %r40;
	add.s32 	%r166, %r891, -16;
	ld.local.u32 	%r1744, [%r891+8];
	ld.local.u32 	%r1745, [%r891+4];
	setp.eq.s32 	%p115, %r165, 0;
	@%p115 bra 	BB11_122;

	shl.b32 	%r892, %r1744, %r165;
	neg.s32 	%r893, %r164;
	and.b32  	%r894, %r893, 31;
	shr.u32 	%r895, %r1745, %r894;
	or.b32  	%r1744, %r895, %r892;
	ld.local.u32 	%r896, [%r166+16];
	shr.u32 	%r897, %r896, %r894;
	shl.b32 	%r898, %r1745, %r165;
	or.b32  	%r1745, %r897, %r898;

BB11_122:
	shr.u32 	%r899, %r1745, 30;
	shl.b32 	%r900, %r1744, 2;
	or.b32  	%r1750, %r899, %r900;
	shl.b32 	%r174, %r1745, 2;
	setp.ne.s32 	%p116, %r174, 0;
	selp.u32 	%r901, 1, 0, %p116;
	add.s32 	%r902, %r901, %r1750;
	setp.gt.u32 	%p117, %r902, -2147483648;
	selp.u32 	%r903, 1, 0, %p117;
	shr.u32 	%r904, %r1744, 30;
	add.s32 	%r905, %r903, %r904;
	neg.s32 	%r906, %r905;
	setp.lt.s32 	%p118, %r162, 0;
	selp.b32 	%r1754, %r906, %r905, %p118;
	@%p117 bra 	BB11_124;

	mov.u32 	%r1749, %r174;
	bra.uni 	BB11_125;

BB11_124:
	not.b32 	%r907, %r1750;
	neg.s32 	%r176, %r174;
	setp.eq.s32 	%p119, %r174, 0;
	selp.u32 	%r908, 1, 0, %p119;
	add.s32 	%r1750, %r908, %r907;
	xor.b32  	%r1746, %r1746, -2147483648;
	mov.u32 	%r1749, %r176;

BB11_125:
	mov.u32 	%r1748, %r1749;
	setp.gt.s32 	%p120, %r1750, 0;
	@%p120 bra 	BB11_127;

	mov.u32 	%r1753, 0;
	bra.uni 	BB11_129;

BB11_127:
	mov.u32 	%r1753, 0;

BB11_128:
	shr.u32 	%r911, %r1748, 31;
	shl.b32 	%r912, %r1750, 1;
	or.b32  	%r1750, %r911, %r912;
	shl.b32 	%r1748, %r1748, 1;
	add.s32 	%r1753, %r1753, -1;
	setp.gt.s32 	%p121, %r1750, 0;
	@%p121 bra 	BB11_128;

BB11_129:
	mul.lo.s32 	%r1752, %r1750, -921707870;
	mov.u32 	%r915, -921707870;
	// inline asm
	mul.hi.u32 	%r913, %r1750, %r915;
	// inline asm
	setp.gt.s32 	%p122, %r913, 0;
	mov.u32 	%r1751, %r913;
	@%p122 bra 	BB11_130;
	bra.uni 	BB11_131;

BB11_130:
	shl.b32 	%r916, %r913, 1;
	shr.u32 	%r917, %r1752, 31;
	or.b32  	%r1751, %r916, %r917;
	mul.lo.s32 	%r1752, %r1750, -1843415740;
	add.s32 	%r1753, %r1753, -1;

BB11_131:
	setp.ne.s32 	%p123, %r1752, 0;
	selp.u32 	%r918, 1, 0, %p123;
	add.s32 	%r919, %r918, %r1751;
	shr.u32 	%r920, %r919, 8;
	shr.u32 	%r921, %r919, 7;
	and.b32  	%r922, %r921, 1;
	shl.b32 	%r923, %r1753, 23;
	add.s32 	%r924, %r923, %r920;
	add.s32 	%r925, %r924, %r922;
	add.s32 	%r926, %r925, 1056964608;
	or.b32  	%r927, %r926, %r1746;
	mov.b32 	 %f1060, %r927;

BB11_132:
	add.s32 	%r199, %r1754, 1;
	and.b32  	%r928, %r199, 1;
	setp.eq.s32 	%p124, %r928, 0;
	mul.rn.f32 	%f71, %f1060, %f1060;
	@%p124 bra 	BB11_134;

	mov.f32 	%f423, 0f37CCF5CE;
	mul.rn.f32 	%f424, %f423, %f71;
	add.f32 	%f425, %f424, 0fBAB6061A;
	mul.rn.f32 	%f426, %f425, %f71;
	add.f32 	%f427, %f426, 0f3D2AAAA5;
	mul.rn.f32 	%f428, %f427, %f71;
	add.f32 	%f429, %f428, 0fBF000000;
	mul.rn.f32 	%f430, %f429, %f71;
	add.f32 	%f1061, %f430, 0f3F800000;
	bra.uni 	BB11_135;

BB11_134:
	mov.f32 	%f431, 0fB94CA1F9;
	mul.rn.f32 	%f432, %f431, %f71;
	add.f32 	%f433, %f432, 0f3C08839E;
	mul.rn.f32 	%f434, %f433, %f71;
	add.f32 	%f435, %f434, 0fBE2AAAA3;
	mul.rn.f32 	%f436, %f435, %f71;
	mul.rn.f32 	%f437, %f436, %f1060;
	add.f32 	%f1061, %f437, %f1060;

BB11_135:
	and.b32  	%r929, %r199, 2;
	setp.eq.s32 	%p125, %r929, 0;
	neg.f32 	%f438, %f1061;
	selp.f32 	%f1103, %f1061, %f438, %p125;
	bra.uni 	BB11_137;

BB11_136:
	mov.f32 	%f1103, %f14;

BB11_137:
	mad.f32 	%f439, %f1103, 0f3E23D70A, 0f3F000000;
	mad.f32 	%f77, %f1103, %f439, 0f3EAE147B;
	mov.f32 	%f1068, %f77;
	bra.uni 	BB11_190;

BB11_138:
	mov.b32 	 %r201, %f78;
	and.b32  	%r1757, %r201, -2147483648;
	shr.u32 	%r203, %r201, 23;
	and.b32  	%r948, %r203, 255;
	add.s32 	%r949, %r948, -128;
	shl.b32 	%r950, %r201, 8;
	or.b32  	%r947, %r950, -2147483648;
	shr.u32 	%r951, %r949, 5;
	mov.u32 	%r952, 4;
	sub.s32 	%r953, %r952, %r951;
	ld.const.u32 	%r931, [__GPU_i2opi_f];
	mul.lo.s32 	%r954, %r931, %r947;
	// inline asm
	mul.hi.u32 	%r930, %r931, %r947;
	// inline asm
	st.local.u32 	[%r40], %r954;
	ld.const.u32 	%r934, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r955, %r934, %r947;
	// inline asm
	mul.hi.u32 	%r933, %r934, %r947;
	// inline asm
	mad.lo.s32 	%r956, %r934, %r947, %r930;
	setp.lt.u32 	%p130, %r956, %r955;
	selp.u32 	%r957, 1, 0, %p130;
	add.s32 	%r958, %r957, %r933;
	st.local.u32 	[%r40+4], %r956;
	ld.const.u32 	%r937, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r959, %r937, %r947;
	// inline asm
	mul.hi.u32 	%r936, %r937, %r947;
	// inline asm
	mad.lo.s32 	%r960, %r937, %r947, %r958;
	setp.lt.u32 	%p131, %r960, %r959;
	selp.u32 	%r961, 1, 0, %p131;
	add.s32 	%r962, %r961, %r936;
	st.local.u32 	[%r40+8], %r960;
	ld.const.u32 	%r940, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r963, %r940, %r947;
	// inline asm
	mul.hi.u32 	%r939, %r940, %r947;
	// inline asm
	mad.lo.s32 	%r964, %r940, %r947, %r962;
	setp.lt.u32 	%p132, %r964, %r963;
	selp.u32 	%r965, 1, 0, %p132;
	add.s32 	%r966, %r965, %r939;
	st.local.u32 	[%r40+12], %r964;
	ld.const.u32 	%r943, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r967, %r943, %r947;
	// inline asm
	mul.hi.u32 	%r942, %r943, %r947;
	// inline asm
	mad.lo.s32 	%r968, %r943, %r947, %r966;
	setp.lt.u32 	%p133, %r968, %r967;
	selp.u32 	%r969, 1, 0, %p133;
	add.s32 	%r970, %r969, %r942;
	st.local.u32 	[%r40+16], %r968;
	ld.const.u32 	%r946, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r971, %r946, %r947;
	// inline asm
	mul.hi.u32 	%r945, %r946, %r947;
	// inline asm
	mad.lo.s32 	%r972, %r946, %r947, %r970;
	setp.lt.u32 	%p134, %r972, %r971;
	selp.u32 	%r973, 1, 0, %p134;
	add.s32 	%r974, %r973, %r945;
	st.local.u32 	[%r40+20], %r972;
	st.local.u32 	[%r40+24], %r974;
	and.b32  	%r204, %r203, 31;
	shl.b32 	%r976, %r953, 2;
	add.s32 	%r977, %r976, %r40;
	add.s32 	%r205, %r977, -16;
	ld.local.u32 	%r1755, [%r977+8];
	ld.local.u32 	%r1756, [%r977+4];
	setp.eq.s32 	%p135, %r204, 0;
	@%p135 bra 	BB11_140;

	shl.b32 	%r978, %r1755, %r204;
	neg.s32 	%r979, %r203;
	and.b32  	%r980, %r979, 31;
	shr.u32 	%r981, %r1756, %r980;
	or.b32  	%r1755, %r981, %r978;
	ld.local.u32 	%r982, [%r205+16];
	shr.u32 	%r983, %r982, %r980;
	shl.b32 	%r984, %r1756, %r204;
	or.b32  	%r1756, %r983, %r984;

BB11_140:
	shr.u32 	%r985, %r1756, 30;
	shl.b32 	%r986, %r1755, 2;
	or.b32  	%r1761, %r985, %r986;
	shl.b32 	%r213, %r1756, 2;
	setp.ne.s32 	%p136, %r213, 0;
	selp.u32 	%r987, 1, 0, %p136;
	add.s32 	%r988, %r987, %r1761;
	setp.gt.u32 	%p137, %r988, -2147483648;
	selp.u32 	%r989, 1, 0, %p137;
	shr.u32 	%r990, %r1755, 30;
	add.s32 	%r991, %r989, %r990;
	neg.s32 	%r992, %r991;
	setp.lt.s32 	%p138, %r201, 0;
	selp.b32 	%r1765, %r992, %r991, %p138;
	@%p137 bra 	BB11_142;

	mov.u32 	%r1760, %r213;
	bra.uni 	BB11_143;

BB11_142:
	not.b32 	%r993, %r1761;
	neg.s32 	%r215, %r213;
	setp.eq.s32 	%p139, %r213, 0;
	selp.u32 	%r994, 1, 0, %p139;
	add.s32 	%r1761, %r994, %r993;
	xor.b32  	%r1757, %r1757, -2147483648;
	mov.u32 	%r1760, %r215;

BB11_143:
	mov.u32 	%r1759, %r1760;
	setp.gt.s32 	%p140, %r1761, 0;
	@%p140 bra 	BB11_145;

	mov.u32 	%r1764, 0;
	bra.uni 	BB11_147;

BB11_145:
	mov.u32 	%r1764, 0;

BB11_146:
	shr.u32 	%r997, %r1759, 31;
	shl.b32 	%r998, %r1761, 1;
	or.b32  	%r1761, %r997, %r998;
	shl.b32 	%r1759, %r1759, 1;
	add.s32 	%r1764, %r1764, -1;
	setp.gt.s32 	%p141, %r1761, 0;
	@%p141 bra 	BB11_146;

BB11_147:
	mul.lo.s32 	%r1763, %r1761, -921707870;
	mov.u32 	%r1001, -921707870;
	// inline asm
	mul.hi.u32 	%r999, %r1761, %r1001;
	// inline asm
	setp.gt.s32 	%p142, %r999, 0;
	mov.u32 	%r1762, %r999;
	@%p142 bra 	BB11_148;
	bra.uni 	BB11_149;

BB11_148:
	shl.b32 	%r1002, %r999, 1;
	shr.u32 	%r1003, %r1763, 31;
	or.b32  	%r1762, %r1002, %r1003;
	mul.lo.s32 	%r1763, %r1761, -1843415740;
	add.s32 	%r1764, %r1764, -1;

BB11_149:
	setp.ne.s32 	%p143, %r1763, 0;
	selp.u32 	%r1004, 1, 0, %p143;
	add.s32 	%r1005, %r1004, %r1762;
	shr.u32 	%r1006, %r1005, 8;
	shr.u32 	%r1007, %r1005, 7;
	and.b32  	%r1008, %r1007, 1;
	shl.b32 	%r1009, %r1764, 23;
	add.s32 	%r1010, %r1009, %r1006;
	add.s32 	%r1011, %r1010, %r1008;
	add.s32 	%r1012, %r1011, 1056964608;
	or.b32  	%r1013, %r1012, %r1757;
	mov.b32 	 %f1062, %r1013;

BB11_150:
	add.s32 	%r238, %r1765, 1;
	and.b32  	%r1014, %r238, 1;
	setp.eq.s32 	%p144, %r1014, 0;
	mul.rn.f32 	%f82, %f1062, %f1062;
	@%p144 bra 	BB11_152;

	mov.f32 	%f457, 0f37CCF5CE;
	mul.rn.f32 	%f458, %f457, %f82;
	add.f32 	%f459, %f458, 0fBAB6061A;
	mul.rn.f32 	%f460, %f459, %f82;
	add.f32 	%f461, %f460, 0f3D2AAAA5;
	mul.rn.f32 	%f462, %f461, %f82;
	add.f32 	%f463, %f462, 0fBF000000;
	mul.rn.f32 	%f464, %f463, %f82;
	add.f32 	%f1063, %f464, 0f3F800000;
	bra.uni 	BB11_153;

BB11_152:
	mov.f32 	%f465, 0fB94CA1F9;
	mul.rn.f32 	%f466, %f465, %f82;
	add.f32 	%f467, %f466, 0f3C08839E;
	mul.rn.f32 	%f468, %f467, %f82;
	add.f32 	%f469, %f468, 0fBE2AAAA3;
	mul.rn.f32 	%f470, %f469, %f82;
	mul.rn.f32 	%f471, %f470, %f1062;
	add.f32 	%f1063, %f471, %f1062;

BB11_153:
	and.b32  	%r1015, %r238, 2;
	setp.eq.s32 	%p145, %r1015, 0;
	neg.f32 	%f472, %f1063;
	selp.f32 	%f1102, %f1063, %f472, %p145;
	bra.uni 	BB11_155;

BB11_154:
	mov.f32 	%f1102, %f14;

BB11_155:
	mad.f32 	%f88, %f1102, 0f3EEB851F, 0f3F0A3D71;
	mov.f32 	%f1068, %f88;
	bra.uni 	BB11_190;

BB11_156:
	mul.f32 	%f89, %f257, 0f40490FDC;
	setp.eq.f32 	%p146, %f89, %f12;
	setp.eq.f32 	%p147, %f89, %f13;
	or.pred  	%p148, %p146, %p147;
	@%p148 bra 	BB11_175;

	// inline asm
	abs.f32 	%f473, %f89;
	// inline asm
	setp.gt.f32 	%p149, %f473, 0f473BA700;
	@%p149 bra 	BB11_159;

	mov.f32 	%f477, 0f3F22F983;
	mul.rn.f32 	%f476, %f89, %f477;
	// inline asm
	cvt.rni.f32.f32 	%f475, %f476;
	// inline asm
	cvt.rzi.s32.f32 	%r1776, %f475;
	cvt.rn.f32.s32 	%f478, %r1776;
	mov.f32 	%f479, 0f3FC90000;
	mul.rn.f32 	%f480, %f478, %f479;
	sub.f32 	%f481, %f89, %f480;
	mov.f32 	%f482, 0f39FD8000;
	mul.rn.f32 	%f483, %f478, %f482;
	sub.f32 	%f484, %f481, %f483;
	mov.f32 	%f485, 0f34A88000;
	mul.rn.f32 	%f486, %f478, %f485;
	sub.f32 	%f487, %f484, %f486;
	mov.f32 	%f488, 0f2E85A309;
	mul.rn.f32 	%f489, %f478, %f488;
	sub.f32 	%f1064, %f487, %f489;
	bra.uni 	BB11_171;

BB11_159:
	mov.b32 	 %r240, %f89;
	and.b32  	%r1768, %r240, -2147483648;
	shr.u32 	%r242, %r240, 23;
	and.b32  	%r1034, %r242, 255;
	add.s32 	%r1035, %r1034, -128;
	shl.b32 	%r1036, %r240, 8;
	or.b32  	%r1033, %r1036, -2147483648;
	shr.u32 	%r1037, %r1035, 5;
	mov.u32 	%r1038, 4;
	sub.s32 	%r1039, %r1038, %r1037;
	ld.const.u32 	%r1017, [__GPU_i2opi_f];
	mul.lo.s32 	%r1040, %r1017, %r1033;
	// inline asm
	mul.hi.u32 	%r1016, %r1017, %r1033;
	// inline asm
	st.local.u32 	[%r40], %r1040;
	ld.const.u32 	%r1020, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1041, %r1020, %r1033;
	// inline asm
	mul.hi.u32 	%r1019, %r1020, %r1033;
	// inline asm
	mad.lo.s32 	%r1042, %r1020, %r1033, %r1016;
	setp.lt.u32 	%p150, %r1042, %r1041;
	selp.u32 	%r1043, 1, 0, %p150;
	add.s32 	%r1044, %r1043, %r1019;
	st.local.u32 	[%r40+4], %r1042;
	ld.const.u32 	%r1023, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1045, %r1023, %r1033;
	// inline asm
	mul.hi.u32 	%r1022, %r1023, %r1033;
	// inline asm
	mad.lo.s32 	%r1046, %r1023, %r1033, %r1044;
	setp.lt.u32 	%p151, %r1046, %r1045;
	selp.u32 	%r1047, 1, 0, %p151;
	add.s32 	%r1048, %r1047, %r1022;
	st.local.u32 	[%r40+8], %r1046;
	ld.const.u32 	%r1026, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1049, %r1026, %r1033;
	// inline asm
	mul.hi.u32 	%r1025, %r1026, %r1033;
	// inline asm
	mad.lo.s32 	%r1050, %r1026, %r1033, %r1048;
	setp.lt.u32 	%p152, %r1050, %r1049;
	selp.u32 	%r1051, 1, 0, %p152;
	add.s32 	%r1052, %r1051, %r1025;
	st.local.u32 	[%r40+12], %r1050;
	ld.const.u32 	%r1029, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1053, %r1029, %r1033;
	// inline asm
	mul.hi.u32 	%r1028, %r1029, %r1033;
	// inline asm
	mad.lo.s32 	%r1054, %r1029, %r1033, %r1052;
	setp.lt.u32 	%p153, %r1054, %r1053;
	selp.u32 	%r1055, 1, 0, %p153;
	add.s32 	%r1056, %r1055, %r1028;
	st.local.u32 	[%r40+16], %r1054;
	ld.const.u32 	%r1032, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1057, %r1032, %r1033;
	// inline asm
	mul.hi.u32 	%r1031, %r1032, %r1033;
	// inline asm
	mad.lo.s32 	%r1058, %r1032, %r1033, %r1056;
	setp.lt.u32 	%p154, %r1058, %r1057;
	selp.u32 	%r1059, 1, 0, %p154;
	add.s32 	%r1060, %r1059, %r1031;
	st.local.u32 	[%r40+20], %r1058;
	st.local.u32 	[%r40+24], %r1060;
	and.b32  	%r243, %r242, 31;
	shl.b32 	%r1062, %r1039, 2;
	add.s32 	%r1063, %r1062, %r40;
	add.s32 	%r244, %r1063, -16;
	ld.local.u32 	%r1766, [%r1063+8];
	ld.local.u32 	%r1767, [%r1063+4];
	setp.eq.s32 	%p155, %r243, 0;
	@%p155 bra 	BB11_161;

	shl.b32 	%r1064, %r1766, %r243;
	neg.s32 	%r1065, %r242;
	and.b32  	%r1066, %r1065, 31;
	shr.u32 	%r1067, %r1767, %r1066;
	or.b32  	%r1766, %r1067, %r1064;
	ld.local.u32 	%r1068, [%r244+16];
	shr.u32 	%r1069, %r1068, %r1066;
	shl.b32 	%r1070, %r1767, %r243;
	or.b32  	%r1767, %r1069, %r1070;

BB11_161:
	shr.u32 	%r1071, %r1767, 30;
	shl.b32 	%r1072, %r1766, 2;
	or.b32  	%r1772, %r1071, %r1072;
	shl.b32 	%r252, %r1767, 2;
	setp.ne.s32 	%p156, %r252, 0;
	selp.u32 	%r1073, 1, 0, %p156;
	add.s32 	%r1074, %r1073, %r1772;
	setp.gt.u32 	%p157, %r1074, -2147483648;
	selp.u32 	%r1075, 1, 0, %p157;
	shr.u32 	%r1076, %r1766, 30;
	add.s32 	%r1077, %r1075, %r1076;
	neg.s32 	%r1078, %r1077;
	setp.lt.s32 	%p158, %r240, 0;
	selp.b32 	%r1776, %r1078, %r1077, %p158;
	@%p157 bra 	BB11_163;

	mov.u32 	%r1771, %r252;
	bra.uni 	BB11_164;

BB11_163:
	not.b32 	%r1079, %r1772;
	neg.s32 	%r254, %r252;
	setp.eq.s32 	%p159, %r252, 0;
	selp.u32 	%r1080, 1, 0, %p159;
	add.s32 	%r1772, %r1080, %r1079;
	xor.b32  	%r1768, %r1768, -2147483648;
	mov.u32 	%r1771, %r254;

BB11_164:
	mov.u32 	%r1770, %r1771;
	setp.gt.s32 	%p160, %r1772, 0;
	@%p160 bra 	BB11_166;

	mov.u32 	%r1775, 0;
	bra.uni 	BB11_168;

BB11_166:
	mov.u32 	%r1775, 0;

BB11_167:
	shr.u32 	%r1083, %r1770, 31;
	shl.b32 	%r1084, %r1772, 1;
	or.b32  	%r1772, %r1083, %r1084;
	shl.b32 	%r1770, %r1770, 1;
	add.s32 	%r1775, %r1775, -1;
	setp.gt.s32 	%p161, %r1772, 0;
	@%p161 bra 	BB11_167;

BB11_168:
	mul.lo.s32 	%r1774, %r1772, -921707870;
	mov.u32 	%r1087, -921707870;
	// inline asm
	mul.hi.u32 	%r1085, %r1772, %r1087;
	// inline asm
	setp.gt.s32 	%p162, %r1085, 0;
	mov.u32 	%r1773, %r1085;
	@%p162 bra 	BB11_169;
	bra.uni 	BB11_170;

BB11_169:
	shl.b32 	%r1088, %r1085, 1;
	shr.u32 	%r1089, %r1774, 31;
	or.b32  	%r1773, %r1088, %r1089;
	mul.lo.s32 	%r1774, %r1772, -1843415740;
	add.s32 	%r1775, %r1775, -1;

BB11_170:
	setp.ne.s32 	%p163, %r1774, 0;
	selp.u32 	%r1090, 1, 0, %p163;
	add.s32 	%r1091, %r1090, %r1773;
	shr.u32 	%r1092, %r1091, 8;
	shr.u32 	%r1093, %r1091, 7;
	and.b32  	%r1094, %r1093, 1;
	shl.b32 	%r1095, %r1775, 23;
	add.s32 	%r1096, %r1095, %r1092;
	add.s32 	%r1097, %r1096, %r1094;
	add.s32 	%r1098, %r1097, 1056964608;
	or.b32  	%r1099, %r1098, %r1768;
	mov.b32 	 %f1064, %r1099;

BB11_171:
	add.s32 	%r277, %r1776, 1;
	and.b32  	%r1100, %r277, 1;
	setp.eq.s32 	%p164, %r1100, 0;
	mul.rn.f32 	%f93, %f1064, %f1064;
	@%p164 bra 	BB11_173;

	mov.f32 	%f490, 0f37CCF5CE;
	mul.rn.f32 	%f491, %f490, %f93;
	add.f32 	%f492, %f491, 0fBAB6061A;
	mul.rn.f32 	%f493, %f492, %f93;
	add.f32 	%f494, %f493, 0f3D2AAAA5;
	mul.rn.f32 	%f495, %f494, %f93;
	add.f32 	%f496, %f495, 0fBF000000;
	mul.rn.f32 	%f497, %f496, %f93;
	add.f32 	%f1065, %f497, 0f3F800000;
	bra.uni 	BB11_174;

BB11_173:
	mov.f32 	%f498, 0fB94CA1F9;
	mul.rn.f32 	%f499, %f498, %f93;
	add.f32 	%f500, %f499, 0f3C08839E;
	mul.rn.f32 	%f501, %f500, %f93;
	add.f32 	%f502, %f501, 0fBE2AAAA3;
	mul.rn.f32 	%f503, %f502, %f93;
	mul.rn.f32 	%f504, %f503, %f1064;
	add.f32 	%f1065, %f504, %f1064;

BB11_174:
	and.b32  	%r1101, %r277, 2;
	setp.eq.s32 	%p165, %r1101, 0;
	neg.f32 	%f505, %f1065;
	selp.f32 	%f1101, %f1065, %f505, %p165;
	bra.uni 	BB11_176;

BB11_175:
	mov.f32 	%f1101, %f14;

BB11_176:
	mad.f32 	%f99, %f1101, 0f3F000000, 0f3F000000;
	mov.f32 	%f1068, %f99;
	bra.uni 	BB11_190;

BB11_177:
	setp.lt.f32 	%p166, %f257, 0f3F800000;
	mov.f32 	%f506, 0f3F800000;
	sub.f32 	%f507, %f506, %f257;
	selp.f32 	%f100, %f507, 0f00000000, %p166;
	mov.f32 	%f1068, %f100;
	bra.uni 	BB11_190;

BB11_178:
	ld.param.u32 	%r1693, [ResizeHorizontalFilter_param_10];
	ld.global.f32 	%f514, [%r1693];
	ld.global.f32 	%f515, [%r1693+8];
	ld.global.f32 	%f516, [%r1693+4];
	mad.f32 	%f517, %f257, %f515, %f516;
	mul.f32 	%f518, %f257, %f517;
	mad.f32 	%f102, %f257, %f518, %f514;
	mov.f32 	%f1068, %f102;
	bra.uni 	BB11_190;

BB11_179:
	setp.neu.f32 	%p169, %f257, 0f00000000;
	@%p169 bra 	BB11_181;

BB11_180:
	mov.f32 	%f1068, %f234;
	bra.uni 	BB11_190;

BB11_181:
	mul.f32 	%f103, %f257, 0f40490FDC;
	setp.eq.f32 	%p170, %f257, %f12;
	@%p170 bra 	BB11_187;

	setp.eq.f32 	%p171, %f257, %f13;
	setp.eq.f32 	%p172, %f257, 0f00000000;
	or.pred  	%p173, %p171, %p172;
	@%p173 bra 	BB11_187;

	mov.f32 	%f524, 0f40000000;
	mul.rn.f32 	%f521, %f524, %f257;
	// inline asm
	cvt.rni.f32.f32 	%f520, %f521;
	// inline asm
	cvt.rzi.s32.f32 	%r1102, %f520;
	neg.f32 	%f525, %f520;
	mul.rn.f32 	%f527, %f525, %f237;
	add.f32 	%f528, %f527, %f257;
	mov.f32 	%f529, 0f40490FDB;
	mul.rn.f32 	%f530, %f528, %f529;
	// inline asm
	abs.f32 	%f522, %f257;
	// inline asm
	setp.gt.f32 	%p174, %f522, 0f4B800000;
	selp.f32 	%f104, 0f00000000, %f530, %p174;
	selp.b32 	%r278, 0, %r1102, %p174;
	and.b32  	%r1103, %r278, 1;
	setp.eq.s32 	%p175, %r1103, 0;
	mul.rn.f32 	%f105, %f104, %f104;
	@%p175 bra 	BB11_185;

	mov.f32 	%f531, 0f37CCF5CE;
	mul.rn.f32 	%f532, %f531, %f105;
	add.f32 	%f533, %f532, 0fBAB6061A;
	mul.rn.f32 	%f534, %f533, %f105;
	add.f32 	%f535, %f534, 0f3D2AAAA5;
	mul.rn.f32 	%f536, %f535, %f105;
	add.f32 	%f537, %f536, 0fBF000000;
	mul.rn.f32 	%f538, %f537, %f105;
	add.f32 	%f1066, %f538, 0f3F800000;
	bra.uni 	BB11_186;

BB11_185:
	mov.f32 	%f539, 0fB94CA1F9;
	mul.rn.f32 	%f540, %f539, %f105;
	add.f32 	%f541, %f540, 0f3C08839E;
	mul.rn.f32 	%f542, %f541, %f105;
	add.f32 	%f543, %f542, 0fBE2AAAA3;
	mul.rn.f32 	%f544, %f543, %f105;
	mul.rn.f32 	%f545, %f544, %f104;
	add.f32 	%f1066, %f545, %f104;

BB11_186:
	and.b32  	%r1104, %r278, 2;
	setp.eq.s32 	%p176, %r1104, 0;
	neg.f32 	%f546, %f1066;
	selp.f32 	%f1067, %f1066, %f546, %p176;
	bra.uni 	BB11_188;

BB11_187:
	mov.f32 	%f547, 0f00000000;
	mul.rn.f32 	%f1067, %f257, %f547;

BB11_188:
	div.full.f32 	%f112, %f1067, %f103;
	mov.f32 	%f1068, %f112;
	bra.uni 	BB11_190;

BB11_189:
	mov.f32 	%f548, 0f00000000;
	mov.f32 	%f1068, %f548;

BB11_190:
	mov.f32 	%f113, %f1068;
	mul.f32 	%f549, %f1059, %f113;
	mul.f32 	%f550, %f549, 0f377BA882;
	mov.f32 	%f552, 0f477FFF00;
	sub.f32 	%f553, %f552, %f1030;
	mul.f32 	%f554, %f550, %f553;
	mad.f32 	%f557, %f554, %f1027, %f1124;
	mad.f32 	%f560, %f554, %f1028, %f1125;
	mad.f32 	%f563, %f554, %f1029, %f1126;
	mad.f32 	%f565, %f549, %f1030, %f1127;
	mov.f32 	%f1124, %f557;
	mov.f32 	%f1125, %f560;
	mov.f32 	%f1126, %f563;
	mov.f32 	%f1127, %f565;
	mad.f32 	%f1110, %f1059, %f113, %f1110;
	mad.f32 	%f1111, %f550, %f553, %f1111;
	add.s32 	%r1778, %r1778, 1;
	add.s32 	%r1777, %r1777, 1;
	setp.lt.u32 	%p177, %r1777, %r574;
	@%p177 bra 	BB11_13;
	bra.uni 	BB11_373;

BB11_191:
	@!%p3 bra 	BB11_372;

	mov.f32 	%f1110, 0f00000000;
	mov.f32 	%f1124, %f1110;
	mov.f32 	%f1125, %f1110;
	mov.f32 	%f1126, %f1110;
	mov.f32 	%f1127, %f1110;

BB11_193:
	shl.b32 	%r1105, %r1778, 4;
	ld.param.u32 	%r1697, [ResizeHorizontalFilter_param_15];
	add.s32 	%r1106, %r1697, %r1105;
	ld.shared.v4.f32 	{%f1015, %f1016, %f1017, %f1018}, [%r1106];
	add.s32 	%r1107, %r1777, %r34;
	cvt.rn.f32.u32 	%f569, %r1107;
	sub.f32 	%f570, %f569, %f15;
	add.f32 	%f571, %f570, 0f3F000000;
	mul.f32 	%f572, %f1050, %f571;
	ld.param.f32 	%f1048, [ResizeHorizontalFilter_param_14];
	div.full.f32 	%f568, %f572, %f1048;
	// inline asm
	abs.f32 	%f567, %f568;
	// inline asm
	@%p1 bra 	BB11_281;

	ld.param.f32 	%f1046, [ResizeHorizontalFilter_param_11];
	mul.f32 	%f118, %f567, %f1046;
	ld.param.u32 	%r1678, [ResizeHorizontalFilter_param_9];
	setp.gt.s32 	%p178, %r1678, 2;
	@%p178 bra 	BB11_201;

	ld.param.u32 	%r1672, [ResizeHorizontalFilter_param_9];
	setp.eq.s32 	%p184, %r1672, 0;
	@%p184 bra 	BB11_281;

	ld.param.u32 	%r1671, [ResizeHorizontalFilter_param_9];
	setp.eq.s32 	%p185, %r1671, 1;
	@%p185 bra 	BB11_269;

	ld.param.u32 	%r1670, [ResizeHorizontalFilter_param_9];
	setp.eq.s32 	%p186, %r1670, 2;
	@%p186 bra 	BB11_198;
	bra.uni 	BB11_280;

BB11_198:
	setp.lt.f32 	%p248, %f118, 0f3F800000;
	@%p248 bra 	BB11_270;

	setp.geu.f32 	%p249, %f118, 0f40000000;
	@%p249 bra 	BB11_280;

	ld.param.u32 	%r1692, [ResizeHorizontalFilter_param_10];
	ld.global.f32 	%f675, [%r1692+24];
	ld.global.f32 	%f676, [%r1692+20];
	mad.f32 	%f677, %f118, %f675, %f676;
	ld.global.f32 	%f678, [%r1692+16];
	mad.f32 	%f679, %f118, %f677, %f678;
	ld.global.f32 	%f680, [%r1692+12];
	mad.f32 	%f1077, %f118, %f679, %f680;
	bra.uni 	BB11_282;

BB11_201:
	ld.param.u32 	%r1677, [ResizeHorizontalFilter_param_9];
	setp.gt.s32 	%p179, %r1677, 4;
	@%p179 bra 	BB11_207;

	ld.param.u32 	%r1674, [ResizeHorizontalFilter_param_9];
	setp.eq.s32 	%p182, %r1674, 3;
	@%p182 bra 	BB11_248;

	ld.param.u32 	%r1673, [ResizeHorizontalFilter_param_9];
	setp.eq.s32 	%p183, %r1673, 4;
	@%p183 bra 	BB11_204;
	bra.uni 	BB11_280;

BB11_204:
	mul.f32 	%f130, %f118, 0f40490FDC;
	setp.eq.f32 	%p207, %f130, %f12;
	setp.eq.f32 	%p208, %f130, %f13;
	or.pred  	%p209, %p207, %p208;
	@%p209 bra 	BB11_246;

	// inline asm
	abs.f32 	%f607, %f130;
	// inline asm
	setp.gt.f32 	%p210, %f607, 0f473BA700;
	@%p210 bra 	BB11_230;

	mov.f32 	%f611, 0f3F22F983;
	mul.rn.f32 	%f610, %f130, %f611;
	// inline asm
	cvt.rni.f32.f32 	%f609, %f610;
	// inline asm
	cvt.rzi.s32.f32 	%r1800, %f609;
	cvt.rn.f32.s32 	%f612, %r1800;
	mov.f32 	%f613, 0f3FC90000;
	mul.rn.f32 	%f614, %f612, %f613;
	sub.f32 	%f615, %f130, %f614;
	mov.f32 	%f616, 0f39FD8000;
	mul.rn.f32 	%f617, %f612, %f616;
	sub.f32 	%f618, %f615, %f617;
	mov.f32 	%f619, 0f34A88000;
	mul.rn.f32 	%f620, %f612, %f619;
	sub.f32 	%f621, %f618, %f620;
	mov.f32 	%f622, 0f2E85A309;
	mul.rn.f32 	%f623, %f612, %f622;
	sub.f32 	%f1071, %f621, %f623;
	bra.uni 	BB11_242;

BB11_207:
	ld.param.u32 	%r1676, [ResizeHorizontalFilter_param_9];
	add.s32 	%r1108, %r1676, -9;
	setp.lt.u32 	%p180, %r1108, 2;
	@%p180 bra 	BB11_271;

	ld.param.u32 	%r1675, [ResizeHorizontalFilter_param_9];
	setp.ne.s32 	%p181, %r1675, 5;
	@%p181 bra 	BB11_280;

	mul.f32 	%f119, %f118, 0f40490FDC;
	setp.eq.f32 	%p187, %f119, %f12;
	setp.eq.f32 	%p188, %f119, %f13;
	or.pred  	%p189, %p187, %p188;
	@%p189 bra 	BB11_228;

	// inline asm
	abs.f32 	%f573, %f119;
	// inline asm
	setp.gt.f32 	%p190, %f573, 0f473BA700;
	@%p190 bra 	BB11_212;

	mov.f32 	%f577, 0f3F22F983;
	mul.rn.f32 	%f576, %f119, %f577;
	// inline asm
	cvt.rni.f32.f32 	%f575, %f576;
	// inline asm
	cvt.rzi.s32.f32 	%r1789, %f575;
	cvt.rn.f32.s32 	%f578, %r1789;
	mov.f32 	%f579, 0f3FC90000;
	mul.rn.f32 	%f580, %f578, %f579;
	sub.f32 	%f581, %f119, %f580;
	mov.f32 	%f582, 0f39FD8000;
	mul.rn.f32 	%f583, %f578, %f582;
	sub.f32 	%f584, %f581, %f583;
	mov.f32 	%f585, 0f34A88000;
	mul.rn.f32 	%f586, %f578, %f585;
	sub.f32 	%f587, %f584, %f586;
	mov.f32 	%f588, 0f2E85A309;
	mul.rn.f32 	%f589, %f578, %f588;
	sub.f32 	%f1069, %f587, %f589;
	bra.uni 	BB11_224;

BB11_212:
	mov.b32 	 %r284, %f119;
	and.b32  	%r1781, %r284, -2147483648;
	shr.u32 	%r286, %r284, 23;
	and.b32  	%r1127, %r286, 255;
	add.s32 	%r1128, %r1127, -128;
	shl.b32 	%r1129, %r284, 8;
	or.b32  	%r1126, %r1129, -2147483648;
	shr.u32 	%r1130, %r1128, 5;
	mov.u32 	%r1131, 4;
	sub.s32 	%r1132, %r1131, %r1130;
	ld.const.u32 	%r1110, [__GPU_i2opi_f];
	mul.lo.s32 	%r1133, %r1110, %r1126;
	// inline asm
	mul.hi.u32 	%r1109, %r1110, %r1126;
	// inline asm
	st.local.u32 	[%r40], %r1133;
	ld.const.u32 	%r1113, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1134, %r1113, %r1126;
	// inline asm
	mul.hi.u32 	%r1112, %r1113, %r1126;
	// inline asm
	mad.lo.s32 	%r1135, %r1113, %r1126, %r1109;
	setp.lt.u32 	%p191, %r1135, %r1134;
	selp.u32 	%r1136, 1, 0, %p191;
	add.s32 	%r1137, %r1136, %r1112;
	st.local.u32 	[%r40+4], %r1135;
	ld.const.u32 	%r1116, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1138, %r1116, %r1126;
	// inline asm
	mul.hi.u32 	%r1115, %r1116, %r1126;
	// inline asm
	mad.lo.s32 	%r1139, %r1116, %r1126, %r1137;
	setp.lt.u32 	%p192, %r1139, %r1138;
	selp.u32 	%r1140, 1, 0, %p192;
	add.s32 	%r1141, %r1140, %r1115;
	st.local.u32 	[%r40+8], %r1139;
	ld.const.u32 	%r1119, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1142, %r1119, %r1126;
	// inline asm
	mul.hi.u32 	%r1118, %r1119, %r1126;
	// inline asm
	mad.lo.s32 	%r1143, %r1119, %r1126, %r1141;
	setp.lt.u32 	%p193, %r1143, %r1142;
	selp.u32 	%r1144, 1, 0, %p193;
	add.s32 	%r1145, %r1144, %r1118;
	st.local.u32 	[%r40+12], %r1143;
	ld.const.u32 	%r1122, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1146, %r1122, %r1126;
	// inline asm
	mul.hi.u32 	%r1121, %r1122, %r1126;
	// inline asm
	mad.lo.s32 	%r1147, %r1122, %r1126, %r1145;
	setp.lt.u32 	%p194, %r1147, %r1146;
	selp.u32 	%r1148, 1, 0, %p194;
	add.s32 	%r1149, %r1148, %r1121;
	st.local.u32 	[%r40+16], %r1147;
	ld.const.u32 	%r1125, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1150, %r1125, %r1126;
	// inline asm
	mul.hi.u32 	%r1124, %r1125, %r1126;
	// inline asm
	mad.lo.s32 	%r1151, %r1125, %r1126, %r1149;
	setp.lt.u32 	%p195, %r1151, %r1150;
	selp.u32 	%r1152, 1, 0, %p195;
	add.s32 	%r1153, %r1152, %r1124;
	st.local.u32 	[%r40+20], %r1151;
	st.local.u32 	[%r40+24], %r1153;
	and.b32  	%r287, %r286, 31;
	shl.b32 	%r1155, %r1132, 2;
	add.s32 	%r1156, %r1155, %r40;
	add.s32 	%r288, %r1156, -16;
	ld.local.u32 	%r1779, [%r1156+8];
	ld.local.u32 	%r1780, [%r1156+4];
	setp.eq.s32 	%p196, %r287, 0;
	@%p196 bra 	BB11_214;

	shl.b32 	%r1157, %r1779, %r287;
	neg.s32 	%r1158, %r286;
	and.b32  	%r1159, %r1158, 31;
	shr.u32 	%r1160, %r1780, %r1159;
	or.b32  	%r1779, %r1160, %r1157;
	ld.local.u32 	%r1161, [%r288+16];
	shr.u32 	%r1162, %r1161, %r1159;
	shl.b32 	%r1163, %r1780, %r287;
	or.b32  	%r1780, %r1162, %r1163;

BB11_214:
	shr.u32 	%r1164, %r1780, 30;
	shl.b32 	%r1165, %r1779, 2;
	or.b32  	%r1785, %r1164, %r1165;
	shl.b32 	%r296, %r1780, 2;
	setp.ne.s32 	%p197, %r296, 0;
	selp.u32 	%r1166, 1, 0, %p197;
	add.s32 	%r1167, %r1166, %r1785;
	setp.gt.u32 	%p198, %r1167, -2147483648;
	selp.u32 	%r1168, 1, 0, %p198;
	shr.u32 	%r1169, %r1779, 30;
	add.s32 	%r1170, %r1168, %r1169;
	neg.s32 	%r1171, %r1170;
	setp.lt.s32 	%p199, %r284, 0;
	selp.b32 	%r1789, %r1171, %r1170, %p199;
	@%p198 bra 	BB11_216;

	mov.u32 	%r1784, %r296;
	bra.uni 	BB11_217;

BB11_216:
	not.b32 	%r1172, %r1785;
	neg.s32 	%r298, %r296;
	setp.eq.s32 	%p200, %r296, 0;
	selp.u32 	%r1173, 1, 0, %p200;
	add.s32 	%r1785, %r1173, %r1172;
	xor.b32  	%r1781, %r1781, -2147483648;
	mov.u32 	%r1784, %r298;

BB11_217:
	mov.u32 	%r1783, %r1784;
	setp.gt.s32 	%p201, %r1785, 0;
	@%p201 bra 	BB11_219;

	mov.u32 	%r1788, 0;
	bra.uni 	BB11_221;

BB11_219:
	mov.u32 	%r1788, 0;

BB11_220:
	shr.u32 	%r1176, %r1783, 31;
	shl.b32 	%r1177, %r1785, 1;
	or.b32  	%r1785, %r1176, %r1177;
	shl.b32 	%r1783, %r1783, 1;
	add.s32 	%r1788, %r1788, -1;
	setp.gt.s32 	%p202, %r1785, 0;
	@%p202 bra 	BB11_220;

BB11_221:
	mul.lo.s32 	%r1787, %r1785, -921707870;
	mov.u32 	%r1180, -921707870;
	// inline asm
	mul.hi.u32 	%r1178, %r1785, %r1180;
	// inline asm
	setp.gt.s32 	%p203, %r1178, 0;
	mov.u32 	%r1786, %r1178;
	@%p203 bra 	BB11_222;
	bra.uni 	BB11_223;

BB11_222:
	shl.b32 	%r1181, %r1178, 1;
	shr.u32 	%r1182, %r1787, 31;
	or.b32  	%r1786, %r1181, %r1182;
	mul.lo.s32 	%r1787, %r1785, -1843415740;
	add.s32 	%r1788, %r1788, -1;

BB11_223:
	setp.ne.s32 	%p204, %r1787, 0;
	selp.u32 	%r1183, 1, 0, %p204;
	add.s32 	%r1184, %r1183, %r1786;
	shr.u32 	%r1185, %r1184, 8;
	shr.u32 	%r1186, %r1184, 7;
	and.b32  	%r1187, %r1186, 1;
	shl.b32 	%r1188, %r1788, 23;
	add.s32 	%r1189, %r1188, %r1185;
	add.s32 	%r1190, %r1189, %r1187;
	add.s32 	%r1191, %r1190, 1056964608;
	or.b32  	%r1192, %r1191, %r1781;
	mov.b32 	 %f1069, %r1192;

BB11_224:
	add.s32 	%r321, %r1789, 1;
	and.b32  	%r1193, %r321, 1;
	setp.eq.s32 	%p205, %r1193, 0;
	mul.rn.f32 	%f123, %f1069, %f1069;
	@%p205 bra 	BB11_226;

	mov.f32 	%f590, 0f37CCF5CE;
	mul.rn.f32 	%f591, %f590, %f123;
	add.f32 	%f592, %f591, 0fBAB6061A;
	mul.rn.f32 	%f593, %f592, %f123;
	add.f32 	%f594, %f593, 0f3D2AAAA5;
	mul.rn.f32 	%f595, %f594, %f123;
	add.f32 	%f596, %f595, 0fBF000000;
	mul.rn.f32 	%f597, %f596, %f123;
	add.f32 	%f1070, %f597, 0f3F800000;
	bra.uni 	BB11_227;

BB11_226:
	mov.f32 	%f598, 0fB94CA1F9;
	mul.rn.f32 	%f599, %f598, %f123;
	add.f32 	%f600, %f599, 0f3C08839E;
	mul.rn.f32 	%f601, %f600, %f123;
	add.f32 	%f602, %f601, 0fBE2AAAA3;
	mul.rn.f32 	%f603, %f602, %f123;
	mul.rn.f32 	%f604, %f603, %f1069;
	add.f32 	%f1070, %f604, %f1069;

BB11_227:
	and.b32  	%r1194, %r321, 2;
	setp.eq.s32 	%p206, %r1194, 0;
	neg.f32 	%f605, %f1070;
	selp.f32 	%f1100, %f1070, %f605, %p206;
	bra.uni 	BB11_229;

BB11_228:
	mov.f32 	%f1100, %f14;

BB11_229:
	mad.f32 	%f606, %f1100, 0f3E23D70A, 0f3F000000;
	mad.f32 	%f1077, %f1100, %f606, 0f3EAE147B;
	bra.uni 	BB11_282;

BB11_230:
	mov.b32 	 %r323, %f130;
	and.b32  	%r1792, %r323, -2147483648;
	shr.u32 	%r325, %r323, 23;
	and.b32  	%r1213, %r325, 255;
	add.s32 	%r1214, %r1213, -128;
	shl.b32 	%r1215, %r323, 8;
	or.b32  	%r1212, %r1215, -2147483648;
	shr.u32 	%r1216, %r1214, 5;
	mov.u32 	%r1217, 4;
	sub.s32 	%r1218, %r1217, %r1216;
	ld.const.u32 	%r1196, [__GPU_i2opi_f];
	mul.lo.s32 	%r1219, %r1196, %r1212;
	// inline asm
	mul.hi.u32 	%r1195, %r1196, %r1212;
	// inline asm
	st.local.u32 	[%r40], %r1219;
	ld.const.u32 	%r1199, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1220, %r1199, %r1212;
	// inline asm
	mul.hi.u32 	%r1198, %r1199, %r1212;
	// inline asm
	mad.lo.s32 	%r1221, %r1199, %r1212, %r1195;
	setp.lt.u32 	%p211, %r1221, %r1220;
	selp.u32 	%r1222, 1, 0, %p211;
	add.s32 	%r1223, %r1222, %r1198;
	st.local.u32 	[%r40+4], %r1221;
	ld.const.u32 	%r1202, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1224, %r1202, %r1212;
	// inline asm
	mul.hi.u32 	%r1201, %r1202, %r1212;
	// inline asm
	mad.lo.s32 	%r1225, %r1202, %r1212, %r1223;
	setp.lt.u32 	%p212, %r1225, %r1224;
	selp.u32 	%r1226, 1, 0, %p212;
	add.s32 	%r1227, %r1226, %r1201;
	st.local.u32 	[%r40+8], %r1225;
	ld.const.u32 	%r1205, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1228, %r1205, %r1212;
	// inline asm
	mul.hi.u32 	%r1204, %r1205, %r1212;
	// inline asm
	mad.lo.s32 	%r1229, %r1205, %r1212, %r1227;
	setp.lt.u32 	%p213, %r1229, %r1228;
	selp.u32 	%r1230, 1, 0, %p213;
	add.s32 	%r1231, %r1230, %r1204;
	st.local.u32 	[%r40+12], %r1229;
	ld.const.u32 	%r1208, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1232, %r1208, %r1212;
	// inline asm
	mul.hi.u32 	%r1207, %r1208, %r1212;
	// inline asm
	mad.lo.s32 	%r1233, %r1208, %r1212, %r1231;
	setp.lt.u32 	%p214, %r1233, %r1232;
	selp.u32 	%r1234, 1, 0, %p214;
	add.s32 	%r1235, %r1234, %r1207;
	st.local.u32 	[%r40+16], %r1233;
	ld.const.u32 	%r1211, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1236, %r1211, %r1212;
	// inline asm
	mul.hi.u32 	%r1210, %r1211, %r1212;
	// inline asm
	mad.lo.s32 	%r1237, %r1211, %r1212, %r1235;
	setp.lt.u32 	%p215, %r1237, %r1236;
	selp.u32 	%r1238, 1, 0, %p215;
	add.s32 	%r1239, %r1238, %r1210;
	st.local.u32 	[%r40+20], %r1237;
	st.local.u32 	[%r40+24], %r1239;
	and.b32  	%r326, %r325, 31;
	shl.b32 	%r1241, %r1218, 2;
	add.s32 	%r1242, %r1241, %r40;
	add.s32 	%r327, %r1242, -16;
	ld.local.u32 	%r1790, [%r1242+8];
	ld.local.u32 	%r1791, [%r1242+4];
	setp.eq.s32 	%p216, %r326, 0;
	@%p216 bra 	BB11_232;

	shl.b32 	%r1243, %r1790, %r326;
	neg.s32 	%r1244, %r325;
	and.b32  	%r1245, %r1244, 31;
	shr.u32 	%r1246, %r1791, %r1245;
	or.b32  	%r1790, %r1246, %r1243;
	ld.local.u32 	%r1247, [%r327+16];
	shr.u32 	%r1248, %r1247, %r1245;
	shl.b32 	%r1249, %r1791, %r326;
	or.b32  	%r1791, %r1248, %r1249;

BB11_232:
	shr.u32 	%r1250, %r1791, 30;
	shl.b32 	%r1251, %r1790, 2;
	or.b32  	%r1796, %r1250, %r1251;
	shl.b32 	%r335, %r1791, 2;
	setp.ne.s32 	%p217, %r335, 0;
	selp.u32 	%r1252, 1, 0, %p217;
	add.s32 	%r1253, %r1252, %r1796;
	setp.gt.u32 	%p218, %r1253, -2147483648;
	selp.u32 	%r1254, 1, 0, %p218;
	shr.u32 	%r1255, %r1790, 30;
	add.s32 	%r1256, %r1254, %r1255;
	neg.s32 	%r1257, %r1256;
	setp.lt.s32 	%p219, %r323, 0;
	selp.b32 	%r1800, %r1257, %r1256, %p219;
	@%p218 bra 	BB11_234;

	mov.u32 	%r1795, %r335;
	bra.uni 	BB11_235;

BB11_234:
	not.b32 	%r1258, %r1796;
	neg.s32 	%r337, %r335;
	setp.eq.s32 	%p220, %r335, 0;
	selp.u32 	%r1259, 1, 0, %p220;
	add.s32 	%r1796, %r1259, %r1258;
	xor.b32  	%r1792, %r1792, -2147483648;
	mov.u32 	%r1795, %r337;

BB11_235:
	mov.u32 	%r1794, %r1795;
	setp.gt.s32 	%p221, %r1796, 0;
	@%p221 bra 	BB11_237;

	mov.u32 	%r1799, 0;
	bra.uni 	BB11_239;

BB11_237:
	mov.u32 	%r1799, 0;

BB11_238:
	shr.u32 	%r1262, %r1794, 31;
	shl.b32 	%r1263, %r1796, 1;
	or.b32  	%r1796, %r1262, %r1263;
	shl.b32 	%r1794, %r1794, 1;
	add.s32 	%r1799, %r1799, -1;
	setp.gt.s32 	%p222, %r1796, 0;
	@%p222 bra 	BB11_238;

BB11_239:
	mul.lo.s32 	%r1798, %r1796, -921707870;
	mov.u32 	%r1266, -921707870;
	// inline asm
	mul.hi.u32 	%r1264, %r1796, %r1266;
	// inline asm
	setp.gt.s32 	%p223, %r1264, 0;
	mov.u32 	%r1797, %r1264;
	@%p223 bra 	BB11_240;
	bra.uni 	BB11_241;

BB11_240:
	shl.b32 	%r1267, %r1264, 1;
	shr.u32 	%r1268, %r1798, 31;
	or.b32  	%r1797, %r1267, %r1268;
	mul.lo.s32 	%r1798, %r1796, -1843415740;
	add.s32 	%r1799, %r1799, -1;

BB11_241:
	setp.ne.s32 	%p224, %r1798, 0;
	selp.u32 	%r1269, 1, 0, %p224;
	add.s32 	%r1270, %r1269, %r1797;
	shr.u32 	%r1271, %r1270, 8;
	shr.u32 	%r1272, %r1270, 7;
	and.b32  	%r1273, %r1272, 1;
	shl.b32 	%r1274, %r1799, 23;
	add.s32 	%r1275, %r1274, %r1271;
	add.s32 	%r1276, %r1275, %r1273;
	add.s32 	%r1277, %r1276, 1056964608;
	or.b32  	%r1278, %r1277, %r1792;
	mov.b32 	 %f1071, %r1278;

BB11_242:
	add.s32 	%r360, %r1800, 1;
	and.b32  	%r1279, %r360, 1;
	setp.eq.s32 	%p225, %r1279, 0;
	mul.rn.f32 	%f134, %f1071, %f1071;
	@%p225 bra 	BB11_244;

	mov.f32 	%f624, 0f37CCF5CE;
	mul.rn.f32 	%f625, %f624, %f134;
	add.f32 	%f626, %f625, 0fBAB6061A;
	mul.rn.f32 	%f627, %f626, %f134;
	add.f32 	%f628, %f627, 0f3D2AAAA5;
	mul.rn.f32 	%f629, %f628, %f134;
	add.f32 	%f630, %f629, 0fBF000000;
	mul.rn.f32 	%f631, %f630, %f134;
	add.f32 	%f1072, %f631, 0f3F800000;
	bra.uni 	BB11_245;

BB11_244:
	mov.f32 	%f632, 0fB94CA1F9;
	mul.rn.f32 	%f633, %f632, %f134;
	add.f32 	%f634, %f633, 0f3C08839E;
	mul.rn.f32 	%f635, %f634, %f134;
	add.f32 	%f636, %f635, 0fBE2AAAA3;
	mul.rn.f32 	%f637, %f636, %f134;
	mul.rn.f32 	%f638, %f637, %f1071;
	add.f32 	%f1072, %f638, %f1071;

BB11_245:
	and.b32  	%r1280, %r360, 2;
	setp.eq.s32 	%p226, %r1280, 0;
	neg.f32 	%f639, %f1072;
	selp.f32 	%f1099, %f1072, %f639, %p226;
	bra.uni 	BB11_247;

BB11_246:
	mov.f32 	%f1099, %f14;

BB11_247:
	mad.f32 	%f1077, %f1099, 0f3EEB851F, 0f3F0A3D71;
	bra.uni 	BB11_282;

BB11_248:
	mul.f32 	%f141, %f118, 0f40490FDC;
	setp.eq.f32 	%p227, %f141, %f12;
	setp.eq.f32 	%p228, %f141, %f13;
	or.pred  	%p229, %p227, %p228;
	@%p229 bra 	BB11_267;

	// inline asm
	abs.f32 	%f640, %f141;
	// inline asm
	setp.gt.f32 	%p230, %f640, 0f473BA700;
	@%p230 bra 	BB11_251;

	mov.f32 	%f644, 0f3F22F983;
	mul.rn.f32 	%f643, %f141, %f644;
	// inline asm
	cvt.rni.f32.f32 	%f642, %f643;
	// inline asm
	cvt.rzi.s32.f32 	%r1811, %f642;
	cvt.rn.f32.s32 	%f645, %r1811;
	mov.f32 	%f646, 0f3FC90000;
	mul.rn.f32 	%f647, %f645, %f646;
	sub.f32 	%f648, %f141, %f647;
	mov.f32 	%f649, 0f39FD8000;
	mul.rn.f32 	%f650, %f645, %f649;
	sub.f32 	%f651, %f648, %f650;
	mov.f32 	%f652, 0f34A88000;
	mul.rn.f32 	%f653, %f645, %f652;
	sub.f32 	%f654, %f651, %f653;
	mov.f32 	%f655, 0f2E85A309;
	mul.rn.f32 	%f656, %f645, %f655;
	sub.f32 	%f1073, %f654, %f656;
	bra.uni 	BB11_263;

BB11_251:
	mov.b32 	 %r362, %f141;
	and.b32  	%r1803, %r362, -2147483648;
	shr.u32 	%r364, %r362, 23;
	and.b32  	%r1299, %r364, 255;
	add.s32 	%r1300, %r1299, -128;
	shl.b32 	%r1301, %r362, 8;
	or.b32  	%r1298, %r1301, -2147483648;
	shr.u32 	%r1302, %r1300, 5;
	mov.u32 	%r1303, 4;
	sub.s32 	%r1304, %r1303, %r1302;
	ld.const.u32 	%r1282, [__GPU_i2opi_f];
	mul.lo.s32 	%r1305, %r1282, %r1298;
	// inline asm
	mul.hi.u32 	%r1281, %r1282, %r1298;
	// inline asm
	st.local.u32 	[%r40], %r1305;
	ld.const.u32 	%r1285, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1306, %r1285, %r1298;
	// inline asm
	mul.hi.u32 	%r1284, %r1285, %r1298;
	// inline asm
	mad.lo.s32 	%r1307, %r1285, %r1298, %r1281;
	setp.lt.u32 	%p231, %r1307, %r1306;
	selp.u32 	%r1308, 1, 0, %p231;
	add.s32 	%r1309, %r1308, %r1284;
	st.local.u32 	[%r40+4], %r1307;
	ld.const.u32 	%r1288, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1310, %r1288, %r1298;
	// inline asm
	mul.hi.u32 	%r1287, %r1288, %r1298;
	// inline asm
	mad.lo.s32 	%r1311, %r1288, %r1298, %r1309;
	setp.lt.u32 	%p232, %r1311, %r1310;
	selp.u32 	%r1312, 1, 0, %p232;
	add.s32 	%r1313, %r1312, %r1287;
	st.local.u32 	[%r40+8], %r1311;
	ld.const.u32 	%r1291, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1314, %r1291, %r1298;
	// inline asm
	mul.hi.u32 	%r1290, %r1291, %r1298;
	// inline asm
	mad.lo.s32 	%r1315, %r1291, %r1298, %r1313;
	setp.lt.u32 	%p233, %r1315, %r1314;
	selp.u32 	%r1316, 1, 0, %p233;
	add.s32 	%r1317, %r1316, %r1290;
	st.local.u32 	[%r40+12], %r1315;
	ld.const.u32 	%r1294, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1318, %r1294, %r1298;
	// inline asm
	mul.hi.u32 	%r1293, %r1294, %r1298;
	// inline asm
	mad.lo.s32 	%r1319, %r1294, %r1298, %r1317;
	setp.lt.u32 	%p234, %r1319, %r1318;
	selp.u32 	%r1320, 1, 0, %p234;
	add.s32 	%r1321, %r1320, %r1293;
	st.local.u32 	[%r40+16], %r1319;
	ld.const.u32 	%r1297, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1322, %r1297, %r1298;
	// inline asm
	mul.hi.u32 	%r1296, %r1297, %r1298;
	// inline asm
	mad.lo.s32 	%r1323, %r1297, %r1298, %r1321;
	setp.lt.u32 	%p235, %r1323, %r1322;
	selp.u32 	%r1324, 1, 0, %p235;
	add.s32 	%r1325, %r1324, %r1296;
	st.local.u32 	[%r40+20], %r1323;
	st.local.u32 	[%r40+24], %r1325;
	and.b32  	%r365, %r364, 31;
	shl.b32 	%r1327, %r1304, 2;
	add.s32 	%r1328, %r1327, %r40;
	add.s32 	%r366, %r1328, -16;
	ld.local.u32 	%r1801, [%r1328+8];
	ld.local.u32 	%r1802, [%r1328+4];
	setp.eq.s32 	%p236, %r365, 0;
	@%p236 bra 	BB11_253;

	shl.b32 	%r1329, %r1801, %r365;
	neg.s32 	%r1330, %r364;
	and.b32  	%r1331, %r1330, 31;
	shr.u32 	%r1332, %r1802, %r1331;
	or.b32  	%r1801, %r1332, %r1329;
	ld.local.u32 	%r1333, [%r366+16];
	shr.u32 	%r1334, %r1333, %r1331;
	shl.b32 	%r1335, %r1802, %r365;
	or.b32  	%r1802, %r1334, %r1335;

BB11_253:
	shr.u32 	%r1336, %r1802, 30;
	shl.b32 	%r1337, %r1801, 2;
	or.b32  	%r1807, %r1336, %r1337;
	shl.b32 	%r374, %r1802, 2;
	setp.ne.s32 	%p237, %r374, 0;
	selp.u32 	%r1338, 1, 0, %p237;
	add.s32 	%r1339, %r1338, %r1807;
	setp.gt.u32 	%p238, %r1339, -2147483648;
	selp.u32 	%r1340, 1, 0, %p238;
	shr.u32 	%r1341, %r1801, 30;
	add.s32 	%r1342, %r1340, %r1341;
	neg.s32 	%r1343, %r1342;
	setp.lt.s32 	%p239, %r362, 0;
	selp.b32 	%r1811, %r1343, %r1342, %p239;
	@%p238 bra 	BB11_255;

	mov.u32 	%r1806, %r374;
	bra.uni 	BB11_256;

BB11_255:
	not.b32 	%r1344, %r1807;
	neg.s32 	%r376, %r374;
	setp.eq.s32 	%p240, %r374, 0;
	selp.u32 	%r1345, 1, 0, %p240;
	add.s32 	%r1807, %r1345, %r1344;
	xor.b32  	%r1803, %r1803, -2147483648;
	mov.u32 	%r1806, %r376;

BB11_256:
	mov.u32 	%r1805, %r1806;
	setp.gt.s32 	%p241, %r1807, 0;
	@%p241 bra 	BB11_258;

	mov.u32 	%r1810, 0;
	bra.uni 	BB11_260;

BB11_258:
	mov.u32 	%r1810, 0;

BB11_259:
	shr.u32 	%r1348, %r1805, 31;
	shl.b32 	%r1349, %r1807, 1;
	or.b32  	%r1807, %r1348, %r1349;
	shl.b32 	%r1805, %r1805, 1;
	add.s32 	%r1810, %r1810, -1;
	setp.gt.s32 	%p242, %r1807, 0;
	@%p242 bra 	BB11_259;

BB11_260:
	mul.lo.s32 	%r1809, %r1807, -921707870;
	mov.u32 	%r1352, -921707870;
	// inline asm
	mul.hi.u32 	%r1350, %r1807, %r1352;
	// inline asm
	setp.gt.s32 	%p243, %r1350, 0;
	mov.u32 	%r1808, %r1350;
	@%p243 bra 	BB11_261;
	bra.uni 	BB11_262;

BB11_261:
	shl.b32 	%r1353, %r1350, 1;
	shr.u32 	%r1354, %r1809, 31;
	or.b32  	%r1808, %r1353, %r1354;
	mul.lo.s32 	%r1809, %r1807, -1843415740;
	add.s32 	%r1810, %r1810, -1;

BB11_262:
	setp.ne.s32 	%p244, %r1809, 0;
	selp.u32 	%r1355, 1, 0, %p244;
	add.s32 	%r1356, %r1355, %r1808;
	shr.u32 	%r1357, %r1356, 8;
	shr.u32 	%r1358, %r1356, 7;
	and.b32  	%r1359, %r1358, 1;
	shl.b32 	%r1360, %r1810, 23;
	add.s32 	%r1361, %r1360, %r1357;
	add.s32 	%r1362, %r1361, %r1359;
	add.s32 	%r1363, %r1362, 1056964608;
	or.b32  	%r1364, %r1363, %r1803;
	mov.b32 	 %f1073, %r1364;

BB11_263:
	add.s32 	%r399, %r1811, 1;
	and.b32  	%r1365, %r399, 1;
	setp.eq.s32 	%p245, %r1365, 0;
	mul.rn.f32 	%f145, %f1073, %f1073;
	@%p245 bra 	BB11_265;

	mov.f32 	%f657, 0f37CCF5CE;
	mul.rn.f32 	%f658, %f657, %f145;
	add.f32 	%f659, %f658, 0fBAB6061A;
	mul.rn.f32 	%f660, %f659, %f145;
	add.f32 	%f661, %f660, 0f3D2AAAA5;
	mul.rn.f32 	%f662, %f661, %f145;
	add.f32 	%f663, %f662, 0fBF000000;
	mul.rn.f32 	%f664, %f663, %f145;
	add.f32 	%f1074, %f664, 0f3F800000;
	bra.uni 	BB11_266;

BB11_265:
	mov.f32 	%f665, 0fB94CA1F9;
	mul.rn.f32 	%f666, %f665, %f145;
	add.f32 	%f667, %f666, 0f3C08839E;
	mul.rn.f32 	%f668, %f667, %f145;
	add.f32 	%f669, %f668, 0fBE2AAAA3;
	mul.rn.f32 	%f670, %f669, %f145;
	mul.rn.f32 	%f671, %f670, %f1073;
	add.f32 	%f1074, %f671, %f1073;

BB11_266:
	and.b32  	%r1366, %r399, 2;
	setp.eq.s32 	%p246, %r1366, 0;
	neg.f32 	%f672, %f1074;
	selp.f32 	%f1098, %f1074, %f672, %p246;
	bra.uni 	BB11_268;

BB11_267:
	mov.f32 	%f1098, %f14;

BB11_268:
	mad.f32 	%f1077, %f1098, 0f3F000000, 0f3F000000;
	bra.uni 	BB11_282;

BB11_269:
	setp.lt.f32 	%p247, %f118, 0f3F800000;
	mov.f32 	%f673, 0f3F800000;
	sub.f32 	%f674, %f673, %f118;
	selp.f32 	%f1077, %f674, 0f00000000, %p247;
	bra.uni 	BB11_282;

BB11_270:
	ld.param.u32 	%r1691, [ResizeHorizontalFilter_param_10];
	ld.global.f32 	%f681, [%r1691];
	ld.global.f32 	%f682, [%r1691+8];
	ld.global.f32 	%f683, [%r1691+4];
	mad.f32 	%f684, %f118, %f682, %f683;
	mul.f32 	%f685, %f118, %f684;
	mad.f32 	%f1077, %f118, %f685, %f681;
	bra.uni 	BB11_282;

BB11_271:
	setp.eq.f32 	%p250, %f118, 0f00000000;
	@%p250 bra 	BB11_281;

	mul.f32 	%f155, %f118, 0f40490FDC;
	setp.eq.f32 	%p251, %f118, %f12;
	@%p251 bra 	BB11_278;

	setp.eq.f32 	%p252, %f118, %f13;
	or.pred  	%p254, %p252, %p250;
	@%p254 bra 	BB11_278;

	mov.f32 	%f690, 0f40000000;
	mul.rn.f32 	%f687, %f690, %f118;
	// inline asm
	cvt.rni.f32.f32 	%f686, %f687;
	// inline asm
	cvt.rzi.s32.f32 	%r1367, %f686;
	neg.f32 	%f691, %f686;
	mul.rn.f32 	%f693, %f691, %f237;
	add.f32 	%f694, %f693, %f118;
	mov.f32 	%f695, 0f40490FDB;
	mul.rn.f32 	%f696, %f694, %f695;
	// inline asm
	abs.f32 	%f688, %f118;
	// inline asm
	setp.gt.f32 	%p255, %f688, 0f4B800000;
	selp.f32 	%f156, 0f00000000, %f696, %p255;
	selp.b32 	%r400, 0, %r1367, %p255;
	and.b32  	%r1368, %r400, 1;
	setp.eq.s32 	%p256, %r1368, 0;
	mul.rn.f32 	%f157, %f156, %f156;
	@%p256 bra 	BB11_276;

	mov.f32 	%f697, 0f37CCF5CE;
	mul.rn.f32 	%f698, %f697, %f157;
	add.f32 	%f699, %f698, 0fBAB6061A;
	mul.rn.f32 	%f700, %f699, %f157;
	add.f32 	%f701, %f700, 0f3D2AAAA5;
	mul.rn.f32 	%f702, %f701, %f157;
	add.f32 	%f703, %f702, 0fBF000000;
	mul.rn.f32 	%f704, %f703, %f157;
	add.f32 	%f1075, %f704, 0f3F800000;
	bra.uni 	BB11_277;

BB11_276:
	mov.f32 	%f705, 0fB94CA1F9;
	mul.rn.f32 	%f706, %f705, %f157;
	add.f32 	%f707, %f706, 0f3C08839E;
	mul.rn.f32 	%f708, %f707, %f157;
	add.f32 	%f709, %f708, 0fBE2AAAA3;
	mul.rn.f32 	%f710, %f709, %f157;
	mul.rn.f32 	%f711, %f710, %f156;
	add.f32 	%f1075, %f711, %f156;

BB11_277:
	and.b32  	%r1369, %r400, 2;
	setp.eq.s32 	%p257, %r1369, 0;
	neg.f32 	%f712, %f1075;
	selp.f32 	%f1076, %f1075, %f712, %p257;
	bra.uni 	BB11_279;

BB11_278:
	mov.f32 	%f713, 0f00000000;
	mul.rn.f32 	%f1076, %f118, %f713;

BB11_279:
	div.full.f32 	%f1077, %f1076, %f155;
	bra.uni 	BB11_282;

BB11_280:
	mov.f32 	%f1077, 0f00000000;
	bra.uni 	BB11_282;

BB11_281:
	mov.f32 	%f1077, 0f3F800000;

BB11_282:
	ld.param.u32 	%r1660, [ResizeHorizontalFilter_param_8];
	setp.gt.s32 	%p258, %r1660, 2;
	@%p258 bra 	BB11_289;

	ld.param.u32 	%r1654, [ResizeHorizontalFilter_param_8];
	setp.eq.s32 	%p264, %r1654, 0;
	@%p264 bra 	BB11_360;

	ld.param.u32 	%r1653, [ResizeHorizontalFilter_param_8];
	setp.eq.s32 	%p265, %r1653, 1;
	@%p265 bra 	BB11_357;

	ld.param.u32 	%r1652, [ResizeHorizontalFilter_param_8];
	setp.eq.s32 	%p266, %r1652, 2;
	@%p266 bra 	BB11_286;
	bra.uni 	BB11_369;

BB11_286:
	setp.lt.f32 	%p328, %f567, 0f3F800000;
	@%p328 bra 	BB11_358;

	setp.geu.f32 	%p329, %f567, 0f40000000;
	@%p329 bra 	BB11_369;

	ld.param.u32 	%r1690, [ResizeHorizontalFilter_param_10];
	ld.global.f32 	%f818, [%r1690+24];
	ld.global.f32 	%f819, [%r1690+20];
	mad.f32 	%f820, %f567, %f818, %f819;
	ld.global.f32 	%f821, [%r1690+16];
	mad.f32 	%f822, %f567, %f820, %f821;
	ld.global.f32 	%f823, [%r1690+12];
	mad.f32 	%f1109, %f567, %f822, %f823;
	bra.uni 	BB11_370;

BB11_289:
	ld.param.u32 	%r1659, [ResizeHorizontalFilter_param_8];
	setp.gt.s32 	%p259, %r1659, 4;
	@%p259 bra 	BB11_295;

	ld.param.u32 	%r1656, [ResizeHorizontalFilter_param_8];
	setp.eq.s32 	%p262, %r1656, 3;
	@%p262 bra 	BB11_336;

	ld.param.u32 	%r1655, [ResizeHorizontalFilter_param_8];
	setp.eq.s32 	%p263, %r1655, 4;
	@%p263 bra 	BB11_292;
	bra.uni 	BB11_369;

BB11_292:
	mul.f32 	%f177, %f567, 0f40490FDC;
	setp.eq.f32 	%p287, %f177, %f12;
	setp.eq.f32 	%p288, %f177, %f13;
	or.pred  	%p289, %p287, %p288;
	@%p289 bra 	BB11_334;

	// inline asm
	abs.f32 	%f750, %f177;
	// inline asm
	setp.gt.f32 	%p290, %f750, 0f473BA700;
	@%p290 bra 	BB11_318;

	mov.f32 	%f754, 0f3F22F983;
	mul.rn.f32 	%f753, %f177, %f754;
	// inline asm
	cvt.rni.f32.f32 	%f752, %f753;
	// inline asm
	cvt.rzi.s32.f32 	%r1833, %f752;
	cvt.rn.f32.s32 	%f755, %r1833;
	mov.f32 	%f756, 0f3FC90000;
	mul.rn.f32 	%f757, %f755, %f756;
	sub.f32 	%f758, %f177, %f757;
	mov.f32 	%f759, 0f39FD8000;
	mul.rn.f32 	%f760, %f755, %f759;
	sub.f32 	%f761, %f758, %f760;
	mov.f32 	%f762, 0f34A88000;
	mul.rn.f32 	%f763, %f755, %f762;
	sub.f32 	%f764, %f761, %f763;
	mov.f32 	%f765, 0f2E85A309;
	mul.rn.f32 	%f766, %f755, %f765;
	sub.f32 	%f1080, %f764, %f766;
	bra.uni 	BB11_330;

BB11_295:
	ld.param.u32 	%r1658, [ResizeHorizontalFilter_param_8];
	add.s32 	%r1370, %r1658, -9;
	setp.lt.u32 	%p260, %r1370, 2;
	@%p260 bra 	BB11_359;

	ld.param.u32 	%r1657, [ResizeHorizontalFilter_param_8];
	setp.ne.s32 	%p261, %r1657, 5;
	@%p261 bra 	BB11_369;

	mul.f32 	%f166, %f567, 0f40490FDC;
	setp.eq.f32 	%p267, %f166, %f12;
	setp.eq.f32 	%p268, %f166, %f13;
	or.pred  	%p269, %p267, %p268;
	@%p269 bra 	BB11_316;

	// inline asm
	abs.f32 	%f716, %f166;
	// inline asm
	setp.gt.f32 	%p270, %f716, 0f473BA700;
	@%p270 bra 	BB11_300;

	mov.f32 	%f720, 0f3F22F983;
	mul.rn.f32 	%f719, %f166, %f720;
	// inline asm
	cvt.rni.f32.f32 	%f718, %f719;
	// inline asm
	cvt.rzi.s32.f32 	%r1822, %f718;
	cvt.rn.f32.s32 	%f721, %r1822;
	mov.f32 	%f722, 0f3FC90000;
	mul.rn.f32 	%f723, %f721, %f722;
	sub.f32 	%f724, %f166, %f723;
	mov.f32 	%f725, 0f39FD8000;
	mul.rn.f32 	%f726, %f721, %f725;
	sub.f32 	%f727, %f724, %f726;
	mov.f32 	%f728, 0f34A88000;
	mul.rn.f32 	%f729, %f721, %f728;
	sub.f32 	%f730, %f727, %f729;
	mov.f32 	%f731, 0f2E85A309;
	mul.rn.f32 	%f732, %f721, %f731;
	sub.f32 	%f1078, %f730, %f732;
	bra.uni 	BB11_312;

BB11_300:
	mov.b32 	 %r402, %f166;
	and.b32  	%r1814, %r402, -2147483648;
	shr.u32 	%r404, %r402, 23;
	and.b32  	%r1389, %r404, 255;
	add.s32 	%r1390, %r1389, -128;
	shl.b32 	%r1391, %r402, 8;
	or.b32  	%r1388, %r1391, -2147483648;
	shr.u32 	%r1392, %r1390, 5;
	mov.u32 	%r1393, 4;
	sub.s32 	%r1394, %r1393, %r1392;
	ld.const.u32 	%r1372, [__GPU_i2opi_f];
	mul.lo.s32 	%r1395, %r1372, %r1388;
	// inline asm
	mul.hi.u32 	%r1371, %r1372, %r1388;
	// inline asm
	st.local.u32 	[%r40], %r1395;
	ld.const.u32 	%r1375, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1396, %r1375, %r1388;
	// inline asm
	mul.hi.u32 	%r1374, %r1375, %r1388;
	// inline asm
	mad.lo.s32 	%r1397, %r1375, %r1388, %r1371;
	setp.lt.u32 	%p271, %r1397, %r1396;
	selp.u32 	%r1398, 1, 0, %p271;
	add.s32 	%r1399, %r1398, %r1374;
	st.local.u32 	[%r40+4], %r1397;
	ld.const.u32 	%r1378, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1400, %r1378, %r1388;
	// inline asm
	mul.hi.u32 	%r1377, %r1378, %r1388;
	// inline asm
	mad.lo.s32 	%r1401, %r1378, %r1388, %r1399;
	setp.lt.u32 	%p272, %r1401, %r1400;
	selp.u32 	%r1402, 1, 0, %p272;
	add.s32 	%r1403, %r1402, %r1377;
	st.local.u32 	[%r40+8], %r1401;
	ld.const.u32 	%r1381, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1404, %r1381, %r1388;
	// inline asm
	mul.hi.u32 	%r1380, %r1381, %r1388;
	// inline asm
	mad.lo.s32 	%r1405, %r1381, %r1388, %r1403;
	setp.lt.u32 	%p273, %r1405, %r1404;
	selp.u32 	%r1406, 1, 0, %p273;
	add.s32 	%r1407, %r1406, %r1380;
	st.local.u32 	[%r40+12], %r1405;
	ld.const.u32 	%r1384, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1408, %r1384, %r1388;
	// inline asm
	mul.hi.u32 	%r1383, %r1384, %r1388;
	// inline asm
	mad.lo.s32 	%r1409, %r1384, %r1388, %r1407;
	setp.lt.u32 	%p274, %r1409, %r1408;
	selp.u32 	%r1410, 1, 0, %p274;
	add.s32 	%r1411, %r1410, %r1383;
	st.local.u32 	[%r40+16], %r1409;
	ld.const.u32 	%r1387, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1412, %r1387, %r1388;
	// inline asm
	mul.hi.u32 	%r1386, %r1387, %r1388;
	// inline asm
	mad.lo.s32 	%r1413, %r1387, %r1388, %r1411;
	setp.lt.u32 	%p275, %r1413, %r1412;
	selp.u32 	%r1414, 1, 0, %p275;
	add.s32 	%r1415, %r1414, %r1386;
	st.local.u32 	[%r40+20], %r1413;
	st.local.u32 	[%r40+24], %r1415;
	and.b32  	%r405, %r404, 31;
	shl.b32 	%r1417, %r1394, 2;
	add.s32 	%r1418, %r1417, %r40;
	add.s32 	%r406, %r1418, -16;
	ld.local.u32 	%r1812, [%r1418+8];
	ld.local.u32 	%r1813, [%r1418+4];
	setp.eq.s32 	%p276, %r405, 0;
	@%p276 bra 	BB11_302;

	shl.b32 	%r1419, %r1812, %r405;
	neg.s32 	%r1420, %r404;
	and.b32  	%r1421, %r1420, 31;
	shr.u32 	%r1422, %r1813, %r1421;
	or.b32  	%r1812, %r1422, %r1419;
	ld.local.u32 	%r1423, [%r406+16];
	shr.u32 	%r1424, %r1423, %r1421;
	shl.b32 	%r1425, %r1813, %r405;
	or.b32  	%r1813, %r1424, %r1425;

BB11_302:
	shr.u32 	%r1426, %r1813, 30;
	shl.b32 	%r1427, %r1812, 2;
	or.b32  	%r1818, %r1426, %r1427;
	shl.b32 	%r414, %r1813, 2;
	setp.ne.s32 	%p277, %r414, 0;
	selp.u32 	%r1428, 1, 0, %p277;
	add.s32 	%r1429, %r1428, %r1818;
	setp.gt.u32 	%p278, %r1429, -2147483648;
	selp.u32 	%r1430, 1, 0, %p278;
	shr.u32 	%r1431, %r1812, 30;
	add.s32 	%r1432, %r1430, %r1431;
	neg.s32 	%r1433, %r1432;
	setp.lt.s32 	%p279, %r402, 0;
	selp.b32 	%r1822, %r1433, %r1432, %p279;
	@%p278 bra 	BB11_304;

	mov.u32 	%r1817, %r414;
	bra.uni 	BB11_305;

BB11_304:
	not.b32 	%r1434, %r1818;
	neg.s32 	%r416, %r414;
	setp.eq.s32 	%p280, %r414, 0;
	selp.u32 	%r1435, 1, 0, %p280;
	add.s32 	%r1818, %r1435, %r1434;
	xor.b32  	%r1814, %r1814, -2147483648;
	mov.u32 	%r1817, %r416;

BB11_305:
	mov.u32 	%r1816, %r1817;
	setp.gt.s32 	%p281, %r1818, 0;
	@%p281 bra 	BB11_307;

	mov.u32 	%r1821, 0;
	bra.uni 	BB11_309;

BB11_307:
	mov.u32 	%r1821, 0;

BB11_308:
	shr.u32 	%r1438, %r1816, 31;
	shl.b32 	%r1439, %r1818, 1;
	or.b32  	%r1818, %r1438, %r1439;
	shl.b32 	%r1816, %r1816, 1;
	add.s32 	%r1821, %r1821, -1;
	setp.gt.s32 	%p282, %r1818, 0;
	@%p282 bra 	BB11_308;

BB11_309:
	mul.lo.s32 	%r1820, %r1818, -921707870;
	mov.u32 	%r1442, -921707870;
	// inline asm
	mul.hi.u32 	%r1440, %r1818, %r1442;
	// inline asm
	setp.gt.s32 	%p283, %r1440, 0;
	mov.u32 	%r1819, %r1440;
	@%p283 bra 	BB11_310;
	bra.uni 	BB11_311;

BB11_310:
	shl.b32 	%r1443, %r1440, 1;
	shr.u32 	%r1444, %r1820, 31;
	or.b32  	%r1819, %r1443, %r1444;
	mul.lo.s32 	%r1820, %r1818, -1843415740;
	add.s32 	%r1821, %r1821, -1;

BB11_311:
	setp.ne.s32 	%p284, %r1820, 0;
	selp.u32 	%r1445, 1, 0, %p284;
	add.s32 	%r1446, %r1445, %r1819;
	shr.u32 	%r1447, %r1446, 8;
	shr.u32 	%r1448, %r1446, 7;
	and.b32  	%r1449, %r1448, 1;
	shl.b32 	%r1450, %r1821, 23;
	add.s32 	%r1451, %r1450, %r1447;
	add.s32 	%r1452, %r1451, %r1449;
	add.s32 	%r1453, %r1452, 1056964608;
	or.b32  	%r1454, %r1453, %r1814;
	mov.b32 	 %f1078, %r1454;

BB11_312:
	add.s32 	%r439, %r1822, 1;
	and.b32  	%r1455, %r439, 1;
	setp.eq.s32 	%p285, %r1455, 0;
	mul.rn.f32 	%f170, %f1078, %f1078;
	@%p285 bra 	BB11_314;

	mov.f32 	%f733, 0f37CCF5CE;
	mul.rn.f32 	%f734, %f733, %f170;
	add.f32 	%f735, %f734, 0fBAB6061A;
	mul.rn.f32 	%f736, %f735, %f170;
	add.f32 	%f737, %f736, 0f3D2AAAA5;
	mul.rn.f32 	%f738, %f737, %f170;
	add.f32 	%f739, %f738, 0fBF000000;
	mul.rn.f32 	%f740, %f739, %f170;
	add.f32 	%f1079, %f740, 0f3F800000;
	bra.uni 	BB11_315;

BB11_314:
	mov.f32 	%f741, 0fB94CA1F9;
	mul.rn.f32 	%f742, %f741, %f170;
	add.f32 	%f743, %f742, 0f3C08839E;
	mul.rn.f32 	%f744, %f743, %f170;
	add.f32 	%f745, %f744, 0fBE2AAAA3;
	mul.rn.f32 	%f746, %f745, %f170;
	mul.rn.f32 	%f747, %f746, %f1078;
	add.f32 	%f1079, %f747, %f1078;

BB11_315:
	and.b32  	%r1456, %r439, 2;
	setp.eq.s32 	%p286, %r1456, 0;
	neg.f32 	%f748, %f1079;
	selp.f32 	%f1097, %f1079, %f748, %p286;
	bra.uni 	BB11_317;

BB11_316:
	mov.f32 	%f1097, %f14;

BB11_317:
	mad.f32 	%f749, %f1097, 0f3E23D70A, 0f3F000000;
	mad.f32 	%f1109, %f1097, %f749, 0f3EAE147B;
	bra.uni 	BB11_370;

BB11_318:
	mov.b32 	 %r441, %f177;
	and.b32  	%r1825, %r441, -2147483648;
	shr.u32 	%r443, %r441, 23;
	and.b32  	%r1475, %r443, 255;
	add.s32 	%r1476, %r1475, -128;
	shl.b32 	%r1477, %r441, 8;
	or.b32  	%r1474, %r1477, -2147483648;
	shr.u32 	%r1478, %r1476, 5;
	mov.u32 	%r1479, 4;
	sub.s32 	%r1480, %r1479, %r1478;
	ld.const.u32 	%r1458, [__GPU_i2opi_f];
	mul.lo.s32 	%r1481, %r1458, %r1474;
	// inline asm
	mul.hi.u32 	%r1457, %r1458, %r1474;
	// inline asm
	st.local.u32 	[%r40], %r1481;
	ld.const.u32 	%r1461, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1482, %r1461, %r1474;
	// inline asm
	mul.hi.u32 	%r1460, %r1461, %r1474;
	// inline asm
	mad.lo.s32 	%r1483, %r1461, %r1474, %r1457;
	setp.lt.u32 	%p291, %r1483, %r1482;
	selp.u32 	%r1484, 1, 0, %p291;
	add.s32 	%r1485, %r1484, %r1460;
	st.local.u32 	[%r40+4], %r1483;
	ld.const.u32 	%r1464, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1486, %r1464, %r1474;
	// inline asm
	mul.hi.u32 	%r1463, %r1464, %r1474;
	// inline asm
	mad.lo.s32 	%r1487, %r1464, %r1474, %r1485;
	setp.lt.u32 	%p292, %r1487, %r1486;
	selp.u32 	%r1488, 1, 0, %p292;
	add.s32 	%r1489, %r1488, %r1463;
	st.local.u32 	[%r40+8], %r1487;
	ld.const.u32 	%r1467, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1490, %r1467, %r1474;
	// inline asm
	mul.hi.u32 	%r1466, %r1467, %r1474;
	// inline asm
	mad.lo.s32 	%r1491, %r1467, %r1474, %r1489;
	setp.lt.u32 	%p293, %r1491, %r1490;
	selp.u32 	%r1492, 1, 0, %p293;
	add.s32 	%r1493, %r1492, %r1466;
	st.local.u32 	[%r40+12], %r1491;
	ld.const.u32 	%r1470, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1494, %r1470, %r1474;
	// inline asm
	mul.hi.u32 	%r1469, %r1470, %r1474;
	// inline asm
	mad.lo.s32 	%r1495, %r1470, %r1474, %r1493;
	setp.lt.u32 	%p294, %r1495, %r1494;
	selp.u32 	%r1496, 1, 0, %p294;
	add.s32 	%r1497, %r1496, %r1469;
	st.local.u32 	[%r40+16], %r1495;
	ld.const.u32 	%r1473, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1498, %r1473, %r1474;
	// inline asm
	mul.hi.u32 	%r1472, %r1473, %r1474;
	// inline asm
	mad.lo.s32 	%r1499, %r1473, %r1474, %r1497;
	setp.lt.u32 	%p295, %r1499, %r1498;
	selp.u32 	%r1500, 1, 0, %p295;
	add.s32 	%r1501, %r1500, %r1472;
	st.local.u32 	[%r40+20], %r1499;
	st.local.u32 	[%r40+24], %r1501;
	and.b32  	%r444, %r443, 31;
	shl.b32 	%r1503, %r1480, 2;
	add.s32 	%r1504, %r1503, %r40;
	add.s32 	%r445, %r1504, -16;
	ld.local.u32 	%r1823, [%r1504+8];
	ld.local.u32 	%r1824, [%r1504+4];
	setp.eq.s32 	%p296, %r444, 0;
	@%p296 bra 	BB11_320;

	shl.b32 	%r1505, %r1823, %r444;
	neg.s32 	%r1506, %r443;
	and.b32  	%r1507, %r1506, 31;
	shr.u32 	%r1508, %r1824, %r1507;
	or.b32  	%r1823, %r1508, %r1505;
	ld.local.u32 	%r1509, [%r445+16];
	shr.u32 	%r1510, %r1509, %r1507;
	shl.b32 	%r1511, %r1824, %r444;
	or.b32  	%r1824, %r1510, %r1511;

BB11_320:
	shr.u32 	%r1512, %r1824, 30;
	shl.b32 	%r1513, %r1823, 2;
	or.b32  	%r1829, %r1512, %r1513;
	shl.b32 	%r453, %r1824, 2;
	setp.ne.s32 	%p297, %r453, 0;
	selp.u32 	%r1514, 1, 0, %p297;
	add.s32 	%r1515, %r1514, %r1829;
	setp.gt.u32 	%p298, %r1515, -2147483648;
	selp.u32 	%r1516, 1, 0, %p298;
	shr.u32 	%r1517, %r1823, 30;
	add.s32 	%r1518, %r1516, %r1517;
	neg.s32 	%r1519, %r1518;
	setp.lt.s32 	%p299, %r441, 0;
	selp.b32 	%r1833, %r1519, %r1518, %p299;
	@%p298 bra 	BB11_322;

	mov.u32 	%r1828, %r453;
	bra.uni 	BB11_323;

BB11_322:
	not.b32 	%r1520, %r1829;
	neg.s32 	%r455, %r453;
	setp.eq.s32 	%p300, %r453, 0;
	selp.u32 	%r1521, 1, 0, %p300;
	add.s32 	%r1829, %r1521, %r1520;
	xor.b32  	%r1825, %r1825, -2147483648;
	mov.u32 	%r1828, %r455;

BB11_323:
	mov.u32 	%r1827, %r1828;
	setp.gt.s32 	%p301, %r1829, 0;
	@%p301 bra 	BB11_325;

	mov.u32 	%r1832, 0;
	bra.uni 	BB11_327;

BB11_325:
	mov.u32 	%r1832, 0;

BB11_326:
	shr.u32 	%r1524, %r1827, 31;
	shl.b32 	%r1525, %r1829, 1;
	or.b32  	%r1829, %r1524, %r1525;
	shl.b32 	%r1827, %r1827, 1;
	add.s32 	%r1832, %r1832, -1;
	setp.gt.s32 	%p302, %r1829, 0;
	@%p302 bra 	BB11_326;

BB11_327:
	mul.lo.s32 	%r1831, %r1829, -921707870;
	mov.u32 	%r1528, -921707870;
	// inline asm
	mul.hi.u32 	%r1526, %r1829, %r1528;
	// inline asm
	setp.gt.s32 	%p303, %r1526, 0;
	mov.u32 	%r1830, %r1526;
	@%p303 bra 	BB11_328;
	bra.uni 	BB11_329;

BB11_328:
	shl.b32 	%r1529, %r1526, 1;
	shr.u32 	%r1530, %r1831, 31;
	or.b32  	%r1830, %r1529, %r1530;
	mul.lo.s32 	%r1831, %r1829, -1843415740;
	add.s32 	%r1832, %r1832, -1;

BB11_329:
	setp.ne.s32 	%p304, %r1831, 0;
	selp.u32 	%r1531, 1, 0, %p304;
	add.s32 	%r1532, %r1531, %r1830;
	shr.u32 	%r1533, %r1532, 8;
	shr.u32 	%r1534, %r1532, 7;
	and.b32  	%r1535, %r1534, 1;
	shl.b32 	%r1536, %r1832, 23;
	add.s32 	%r1537, %r1536, %r1533;
	add.s32 	%r1538, %r1537, %r1535;
	add.s32 	%r1539, %r1538, 1056964608;
	or.b32  	%r1540, %r1539, %r1825;
	mov.b32 	 %f1080, %r1540;

BB11_330:
	add.s32 	%r478, %r1833, 1;
	and.b32  	%r1541, %r478, 1;
	setp.eq.s32 	%p305, %r1541, 0;
	mul.rn.f32 	%f181, %f1080, %f1080;
	@%p305 bra 	BB11_332;

	mov.f32 	%f767, 0f37CCF5CE;
	mul.rn.f32 	%f768, %f767, %f181;
	add.f32 	%f769, %f768, 0fBAB6061A;
	mul.rn.f32 	%f770, %f769, %f181;
	add.f32 	%f771, %f770, 0f3D2AAAA5;
	mul.rn.f32 	%f772, %f771, %f181;
	add.f32 	%f773, %f772, 0fBF000000;
	mul.rn.f32 	%f774, %f773, %f181;
	add.f32 	%f1081, %f774, 0f3F800000;
	bra.uni 	BB11_333;

BB11_332:
	mov.f32 	%f775, 0fB94CA1F9;
	mul.rn.f32 	%f776, %f775, %f181;
	add.f32 	%f777, %f776, 0f3C08839E;
	mul.rn.f32 	%f778, %f777, %f181;
	add.f32 	%f779, %f778, 0fBE2AAAA3;
	mul.rn.f32 	%f780, %f779, %f181;
	mul.rn.f32 	%f781, %f780, %f1080;
	add.f32 	%f1081, %f781, %f1080;

BB11_333:
	and.b32  	%r1542, %r478, 2;
	setp.eq.s32 	%p306, %r1542, 0;
	neg.f32 	%f782, %f1081;
	selp.f32 	%f1096, %f1081, %f782, %p306;
	bra.uni 	BB11_335;

BB11_334:
	mov.f32 	%f1096, %f14;

BB11_335:
	mad.f32 	%f1109, %f1096, 0f3EEB851F, 0f3F0A3D71;
	bra.uni 	BB11_370;

BB11_336:
	mul.f32 	%f188, %f567, 0f40490FDC;
	setp.eq.f32 	%p307, %f188, %f12;
	setp.eq.f32 	%p308, %f188, %f13;
	or.pred  	%p309, %p307, %p308;
	@%p309 bra 	BB11_355;

	// inline asm
	abs.f32 	%f783, %f188;
	// inline asm
	setp.gt.f32 	%p310, %f783, 0f473BA700;
	@%p310 bra 	BB11_339;

	mov.f32 	%f787, 0f3F22F983;
	mul.rn.f32 	%f786, %f188, %f787;
	// inline asm
	cvt.rni.f32.f32 	%f785, %f786;
	// inline asm
	cvt.rzi.s32.f32 	%r1844, %f785;
	cvt.rn.f32.s32 	%f788, %r1844;
	mov.f32 	%f789, 0f3FC90000;
	mul.rn.f32 	%f790, %f788, %f789;
	sub.f32 	%f791, %f188, %f790;
	mov.f32 	%f792, 0f39FD8000;
	mul.rn.f32 	%f793, %f788, %f792;
	sub.f32 	%f794, %f791, %f793;
	mov.f32 	%f795, 0f34A88000;
	mul.rn.f32 	%f796, %f788, %f795;
	sub.f32 	%f797, %f794, %f796;
	mov.f32 	%f798, 0f2E85A309;
	mul.rn.f32 	%f799, %f788, %f798;
	sub.f32 	%f1082, %f797, %f799;
	bra.uni 	BB11_351;

BB11_339:
	mov.b32 	 %r480, %f188;
	and.b32  	%r1836, %r480, -2147483648;
	shr.u32 	%r482, %r480, 23;
	and.b32  	%r1561, %r482, 255;
	add.s32 	%r1562, %r1561, -128;
	shl.b32 	%r1563, %r480, 8;
	or.b32  	%r1560, %r1563, -2147483648;
	shr.u32 	%r1564, %r1562, 5;
	mov.u32 	%r1565, 4;
	sub.s32 	%r1566, %r1565, %r1564;
	ld.const.u32 	%r1544, [__GPU_i2opi_f];
	mul.lo.s32 	%r1567, %r1544, %r1560;
	// inline asm
	mul.hi.u32 	%r1543, %r1544, %r1560;
	// inline asm
	st.local.u32 	[%r40], %r1567;
	ld.const.u32 	%r1547, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1568, %r1547, %r1560;
	// inline asm
	mul.hi.u32 	%r1546, %r1547, %r1560;
	// inline asm
	mad.lo.s32 	%r1569, %r1547, %r1560, %r1543;
	setp.lt.u32 	%p311, %r1569, %r1568;
	selp.u32 	%r1570, 1, 0, %p311;
	add.s32 	%r1571, %r1570, %r1546;
	st.local.u32 	[%r40+4], %r1569;
	ld.const.u32 	%r1550, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1572, %r1550, %r1560;
	// inline asm
	mul.hi.u32 	%r1549, %r1550, %r1560;
	// inline asm
	mad.lo.s32 	%r1573, %r1550, %r1560, %r1571;
	setp.lt.u32 	%p312, %r1573, %r1572;
	selp.u32 	%r1574, 1, 0, %p312;
	add.s32 	%r1575, %r1574, %r1549;
	st.local.u32 	[%r40+8], %r1573;
	ld.const.u32 	%r1553, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1576, %r1553, %r1560;
	// inline asm
	mul.hi.u32 	%r1552, %r1553, %r1560;
	// inline asm
	mad.lo.s32 	%r1577, %r1553, %r1560, %r1575;
	setp.lt.u32 	%p313, %r1577, %r1576;
	selp.u32 	%r1578, 1, 0, %p313;
	add.s32 	%r1579, %r1578, %r1552;
	st.local.u32 	[%r40+12], %r1577;
	ld.const.u32 	%r1556, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1580, %r1556, %r1560;
	// inline asm
	mul.hi.u32 	%r1555, %r1556, %r1560;
	// inline asm
	mad.lo.s32 	%r1581, %r1556, %r1560, %r1579;
	setp.lt.u32 	%p314, %r1581, %r1580;
	selp.u32 	%r1582, 1, 0, %p314;
	add.s32 	%r1583, %r1582, %r1555;
	st.local.u32 	[%r40+16], %r1581;
	ld.const.u32 	%r1559, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1584, %r1559, %r1560;
	// inline asm
	mul.hi.u32 	%r1558, %r1559, %r1560;
	// inline asm
	mad.lo.s32 	%r1585, %r1559, %r1560, %r1583;
	setp.lt.u32 	%p315, %r1585, %r1584;
	selp.u32 	%r1586, 1, 0, %p315;
	add.s32 	%r1587, %r1586, %r1558;
	st.local.u32 	[%r40+20], %r1585;
	st.local.u32 	[%r40+24], %r1587;
	and.b32  	%r483, %r482, 31;
	shl.b32 	%r1589, %r1566, 2;
	add.s32 	%r1590, %r1589, %r40;
	add.s32 	%r484, %r1590, -16;
	ld.local.u32 	%r1834, [%r1590+8];
	ld.local.u32 	%r1835, [%r1590+4];
	setp.eq.s32 	%p316, %r483, 0;
	@%p316 bra 	BB11_341;

	shl.b32 	%r1591, %r1834, %r483;
	neg.s32 	%r1592, %r482;
	and.b32  	%r1593, %r1592, 31;
	shr.u32 	%r1594, %r1835, %r1593;
	or.b32  	%r1834, %r1594, %r1591;
	ld.local.u32 	%r1595, [%r484+16];
	shr.u32 	%r1596, %r1595, %r1593;
	shl.b32 	%r1597, %r1835, %r483;
	or.b32  	%r1835, %r1596, %r1597;

BB11_341:
	shr.u32 	%r1598, %r1835, 30;
	shl.b32 	%r1599, %r1834, 2;
	or.b32  	%r1840, %r1598, %r1599;
	shl.b32 	%r492, %r1835, 2;
	setp.ne.s32 	%p317, %r492, 0;
	selp.u32 	%r1600, 1, 0, %p317;
	add.s32 	%r1601, %r1600, %r1840;
	setp.gt.u32 	%p318, %r1601, -2147483648;
	selp.u32 	%r1602, 1, 0, %p318;
	shr.u32 	%r1603, %r1834, 30;
	add.s32 	%r1604, %r1602, %r1603;
	neg.s32 	%r1605, %r1604;
	setp.lt.s32 	%p319, %r480, 0;
	selp.b32 	%r1844, %r1605, %r1604, %p319;
	@%p318 bra 	BB11_343;

	mov.u32 	%r1839, %r492;
	bra.uni 	BB11_344;

BB11_343:
	not.b32 	%r1606, %r1840;
	neg.s32 	%r494, %r492;
	setp.eq.s32 	%p320, %r492, 0;
	selp.u32 	%r1607, 1, 0, %p320;
	add.s32 	%r1840, %r1607, %r1606;
	xor.b32  	%r1836, %r1836, -2147483648;
	mov.u32 	%r1839, %r494;

BB11_344:
	mov.u32 	%r1838, %r1839;
	setp.gt.s32 	%p321, %r1840, 0;
	@%p321 bra 	BB11_346;

	mov.u32 	%r1843, 0;
	bra.uni 	BB11_348;

BB11_346:
	mov.u32 	%r1843, 0;

BB11_347:
	shr.u32 	%r1610, %r1838, 31;
	shl.b32 	%r1611, %r1840, 1;
	or.b32  	%r1840, %r1610, %r1611;
	shl.b32 	%r1838, %r1838, 1;
	add.s32 	%r1843, %r1843, -1;
	setp.gt.s32 	%p322, %r1840, 0;
	@%p322 bra 	BB11_347;

BB11_348:
	mul.lo.s32 	%r1842, %r1840, -921707870;
	mov.u32 	%r1614, -921707870;
	// inline asm
	mul.hi.u32 	%r1612, %r1840, %r1614;
	// inline asm
	setp.gt.s32 	%p323, %r1612, 0;
	mov.u32 	%r1841, %r1612;
	@%p323 bra 	BB11_349;
	bra.uni 	BB11_350;

BB11_349:
	shl.b32 	%r1615, %r1612, 1;
	shr.u32 	%r1616, %r1842, 31;
	or.b32  	%r1841, %r1615, %r1616;
	mul.lo.s32 	%r1842, %r1840, -1843415740;
	add.s32 	%r1843, %r1843, -1;

BB11_350:
	setp.ne.s32 	%p324, %r1842, 0;
	selp.u32 	%r1617, 1, 0, %p324;
	add.s32 	%r1618, %r1617, %r1841;
	shr.u32 	%r1619, %r1618, 8;
	shr.u32 	%r1620, %r1618, 7;
	and.b32  	%r1621, %r1620, 1;
	shl.b32 	%r1622, %r1843, 23;
	add.s32 	%r1623, %r1622, %r1619;
	add.s32 	%r1624, %r1623, %r1621;
	add.s32 	%r1625, %r1624, 1056964608;
	or.b32  	%r1626, %r1625, %r1836;
	mov.b32 	 %f1082, %r1626;

BB11_351:
	add.s32 	%r517, %r1844, 1;
	and.b32  	%r1627, %r517, 1;
	setp.eq.s32 	%p325, %r1627, 0;
	mul.rn.f32 	%f192, %f1082, %f1082;
	@%p325 bra 	BB11_353;

	mov.f32 	%f800, 0f37CCF5CE;
	mul.rn.f32 	%f801, %f800, %f192;
	add.f32 	%f802, %f801, 0fBAB6061A;
	mul.rn.f32 	%f803, %f802, %f192;
	add.f32 	%f804, %f803, 0f3D2AAAA5;
	mul.rn.f32 	%f805, %f804, %f192;
	add.f32 	%f806, %f805, 0fBF000000;
	mul.rn.f32 	%f807, %f806, %f192;
	add.f32 	%f1083, %f807, 0f3F800000;
	bra.uni 	BB11_354;

BB11_353:
	mov.f32 	%f808, 0fB94CA1F9;
	mul.rn.f32 	%f809, %f808, %f192;
	add.f32 	%f810, %f809, 0f3C08839E;
	mul.rn.f32 	%f811, %f810, %f192;
	add.f32 	%f812, %f811, 0fBE2AAAA3;
	mul.rn.f32 	%f813, %f812, %f192;
	mul.rn.f32 	%f814, %f813, %f1082;
	add.f32 	%f1083, %f814, %f1082;

BB11_354:
	and.b32  	%r1628, %r517, 2;
	setp.eq.s32 	%p326, %r1628, 0;
	neg.f32 	%f815, %f1083;
	selp.f32 	%f196, %f1083, %f815, %p326;
	mov.f32 	%f1095, %f196;
	bra.uni 	BB11_356;

BB11_355:
	mov.f32 	%f1095, %f14;

BB11_356:
	mov.f32 	%f197, %f1095;
	mad.f32 	%f1109, %f197, 0f3F000000, 0f3F000000;
	bra.uni 	BB11_370;

BB11_357:
	setp.lt.f32 	%p327, %f567, 0f3F800000;
	mov.f32 	%f816, 0f3F800000;
	sub.f32 	%f817, %f816, %f567;
	selp.f32 	%f1109, %f817, 0f00000000, %p327;
	bra.uni 	BB11_370;

BB11_358:
	ld.param.u32 	%r1689, [ResizeHorizontalFilter_param_10];
	ld.global.f32 	%f824, [%r1689];
	ld.global.f32 	%f825, [%r1689+8];
	ld.global.f32 	%f826, [%r1689+4];
	mad.f32 	%f827, %f567, %f825, %f826;
	mul.f32 	%f828, %f567, %f827;
	mad.f32 	%f1109, %f567, %f828, %f824;
	bra.uni 	BB11_370;

BB11_359:
	setp.neu.f32 	%p330, %f567, 0f00000000;
	@%p330 bra 	BB11_361;

BB11_360:
	mov.f32 	%f1109, 0f3F800000;
	bra.uni 	BB11_370;

BB11_361:
	mul.f32 	%f202, %f567, 0f40490FDC;
	setp.eq.f32 	%p331, %f567, %f12;
	@%p331 bra 	BB11_367;

	setp.eq.f32 	%p332, %f567, %f13;
	setp.eq.f32 	%p333, %f567, 0f00000000;
	or.pred  	%p334, %p332, %p333;
	@%p334 bra 	BB11_367;

	mov.f32 	%f834, 0f40000000;
	mul.rn.f32 	%f831, %f834, %f567;
	// inline asm
	cvt.rni.f32.f32 	%f830, %f831;
	// inline asm
	cvt.rzi.s32.f32 	%r1629, %f830;
	neg.f32 	%f835, %f830;
	mul.rn.f32 	%f837, %f835, %f237;
	add.f32 	%f838, %f837, %f567;
	mov.f32 	%f839, 0f40490FDB;
	mul.rn.f32 	%f840, %f838, %f839;
	// inline asm
	abs.f32 	%f832, %f567;
	// inline asm
	setp.gt.f32 	%p335, %f832, 0f4B800000;
	selp.f32 	%f203, 0f00000000, %f840, %p335;
	selp.b32 	%r518, 0, %r1629, %p335;
	and.b32  	%r1630, %r518, 1;
	setp.eq.s32 	%p336, %r1630, 0;
	mul.rn.f32 	%f204, %f203, %f203;
	@%p336 bra 	BB11_365;

	mov.f32 	%f841, 0f37CCF5CE;
	mul.rn.f32 	%f842, %f841, %f204;
	add.f32 	%f843, %f842, 0fBAB6061A;
	mul.rn.f32 	%f844, %f843, %f204;
	add.f32 	%f845, %f844, 0f3D2AAAA5;
	mul.rn.f32 	%f846, %f845, %f204;
	add.f32 	%f847, %f846, 0fBF000000;
	mul.rn.f32 	%f848, %f847, %f204;
	add.f32 	%f1107, %f848, 0f3F800000;
	bra.uni 	BB11_366;

BB11_365:
	mov.f32 	%f849, 0fB94CA1F9;
	mul.rn.f32 	%f850, %f849, %f204;
	add.f32 	%f851, %f850, 0f3C08839E;
	mul.rn.f32 	%f852, %f851, %f204;
	add.f32 	%f853, %f852, 0fBE2AAAA3;
	mul.rn.f32 	%f854, %f853, %f204;
	mul.rn.f32 	%f855, %f854, %f203;
	add.f32 	%f1107, %f855, %f203;

BB11_366:
	and.b32  	%r1631, %r518, 2;
	setp.eq.s32 	%p337, %r1631, 0;
	neg.f32 	%f856, %f1107;
	selp.f32 	%f1108, %f1107, %f856, %p337;
	bra.uni 	BB11_368;

BB11_367:
	mov.f32 	%f857, 0f00000000;
	mul.rn.f32 	%f1108, %f567, %f857;

BB11_368:
	div.full.f32 	%f1109, %f1108, %f202;
	bra.uni 	BB11_370;

BB11_369:
	mov.f32 	%f1109, 0f00000000;

BB11_370:
	mul.f32 	%f859, %f1077, %f1109;
	mad.f32 	%f1124, %f859, %f1015, %f1124;
	mad.f32 	%f1125, %f859, %f1016, %f1125;
	mad.f32 	%f1126, %f859, %f1017, %f1126;
	mad.f32 	%f1127, %f859, %f1018, %f1127;
	mad.f32 	%f1110, %f1077, %f1109, %f1110;
	add.s32 	%r1778, %r1778, 1;
	add.s32 	%r1777, %r1777, 1;
	setp.lt.u32 	%p338, %r1777, %r574;
	@%p338 bra 	BB11_193;

	mov.f32 	%f1111, 0f00000000;
	bra.uni 	BB11_373;

BB11_372:
	mov.f32 	%f1111, 0f00000000;
	mov.f32 	%f1124, %f1111;
	mov.f32 	%f1125, %f1111;
	mov.f32 	%f1126, %f1111;
	mov.f32 	%f1127, %f1111;
	mov.f32 	%f1110, %f1111;

BB11_373:
	shl.b32 	%r1632, %r563, 4;
	ld.param.u32 	%r1704, [ResizeHorizontalFilter_param_19];
	add.s32 	%r521, %r1704, %r1632;
	shl.b32 	%r1633, %r563, 2;
	ld.param.u32 	%r1706, [ResizeHorizontalFilter_param_20];
	add.s32 	%r522, %r1706, %r1633;
	ld.param.u32 	%r1708, [ResizeHorizontalFilter_param_21];
	add.s32 	%r523, %r1708, %r1633;
	setp.lt.u32 	%p4, %r563, %r30;
	setp.ge.u32 	%p339, %r563, %r30;
	@%p339 bra 	BB11_376;

	mov.f32 	%f866, 0f00000000;
	st.shared.v4.f32 	[%r521], {%f866, %f866, %f866, %f866};
	mov.u32 	%r1634, 0;
	st.shared.u32 	[%r522], %r1634;
	ld.param.u32 	%r1648, [ResizeHorizontalFilter_param_3];
	setp.eq.s32 	%p340, %r1648, 0;
	@%p340 bra 	BB11_376;

	st.shared.u32 	[%r523], %r1634;

BB11_376:
	bar.sync 	0;
	setp.eq.s32 	%p341, %r32, 0;
	@%p341 bra 	BB11_383;

	shl.b32 	%r1637, %r33, 4;
	ld.param.u32 	%r1703, [ResizeHorizontalFilter_param_19];
	add.s32 	%r524, %r1703, %r1637;
	shl.b32 	%r1638, %r33, 2;
	ld.param.u32 	%r1705, [ResizeHorizontalFilter_param_20];
	add.s32 	%r525, %r1705, %r1638;
	ld.param.u32 	%r1707, [ResizeHorizontalFilter_param_21];
	add.s32 	%r526, %r1707, %r1638;
	mov.u32 	%r1845, 0;

BB11_378:
	@%p2 bra 	BB11_382;

	rem.u32 	%r1639, %r563, %r32;
	setp.ne.s32 	%p342, %r1845, %r1639;
	@%p342 bra 	BB11_382;

	ld.shared.v4.f32 	{%f975, %f976, %f977, %f978}, [%r524];
	add.f32 	%f979, %f975, %f1124;
	add.f32 	%f980, %f976, %f1125;
	add.f32 	%f981, %f977, %f1126;
	add.f32 	%f982, %f978, %f1127;
	st.shared.v4.f32 	[%r524], {%f979, %f980, %f981, %f982};
	ld.shared.f32 	%f867, [%r525];
	add.f32 	%f868, %f867, %f1110;
	st.shared.f32 	[%r525], %f868;
	ld.param.u32 	%r1647, [ResizeHorizontalFilter_param_3];
	setp.eq.s32 	%p343, %r1647, 0;
	@%p343 bra 	BB11_382;

	ld.shared.f32 	%f869, [%r526];
	add.f32 	%f870, %f869, %f1111;
	st.shared.f32 	[%r526], %f870;

BB11_382:
	bar.sync 	0;
	add.s32 	%r1845, %r1845, 1;
	setp.lt.u32 	%p344, %r1845, %r32;
	@%p344 bra 	BB11_378;

BB11_383:
	@!%p4 bra 	BB11_400;

	ld.shared.f32 	%f216, [%r522];
	setp.neu.f32 	%p345, %f216, 0f00000000;
	setp.neu.f32 	%p346, %f216, 0f3F800000;
	and.pred  	%p5, %p345, %p346;
	add.s32 	%r1640, %r29, %r27;
	add.s32 	%r1641, %r1640, %r563;
	shl.b32 	%r1642, %r1641, 4;
	ld.param.u32 	%r1650, [ResizeHorizontalFilter_param_5];
	add.s32 	%r529, %r1650, %r1642;
	ld.param.u32 	%r1646, [ResizeHorizontalFilter_param_3];
	setp.eq.s32 	%p347, %r1646, 0;
	@%p347 bra 	BB11_394;

	ld.shared.f32 	%f1113, [%r523];
	ld.shared.v4.f32 	{%f1120, %f1121, %f1122, %f1123}, [%r521];
	@%p5 bra 	BB11_386;
	bra.uni 	BB11_390;

BB11_386:
	setp.lt.f32 	%p348, %f216, 0f00000000;
	selp.f32 	%f218, 0fBF800000, 0f3F800000, %p348;
	mul.f32 	%f871, %f218, %f216;
	setp.ltu.f32 	%p349, %f871, 0f00000000;
	@%p349 bra 	BB11_388;

	rcp.approx.f32 	%f1112, %f216;
	bra.uni 	BB11_389;

BB11_388:
	mul.f32 	%f1112, %f218, 0f7F800000;

BB11_389:
	mul.f32 	%f1120, %f1120, %f1112;
	mul.f32 	%f1121, %f1121, %f1112;
	mul.f32 	%f1122, %f1122, %f1112;
	mul.f32 	%f1123, %f1123, %f1112;
	mul.f32 	%f1113, %f1113, %f1112;

BB11_390:
	setp.lt.f32 	%p350, %f1113, 0f00000000;
	selp.f32 	%f224, 0fBF800000, 0f3F800000, %p350;
	mul.f32 	%f875, %f224, %f1113;
	setp.ltu.f32 	%p351, %f875, 0f00000000;
	@%p351 bra 	BB11_392;

	rcp.approx.f32 	%f1114, %f1113;
	bra.uni 	BB11_393;

BB11_392:
	mul.f32 	%f1114, %f224, 0f7F800000;

BB11_393:
	mul.f32 	%f877, %f1114, %f1120;
	mov.f32 	%f878, 0f00000000;
	max.f32 	%f879, %f877, %f878;
	mov.f32 	%f880, 0f477FFF00;
	min.f32 	%f881, %f879, %f880;
	add.f32 	%f882, %f881, 0f3F000000;
	mul.f32 	%f884, %f1114, %f1121;
	max.f32 	%f885, %f884, %f878;
	min.f32 	%f886, %f885, %f880;
	add.f32 	%f887, %f886, 0f3F000000;
	mul.f32 	%f889, %f1114, %f1122;
	max.f32 	%f890, %f889, %f878;
	min.f32 	%f891, %f890, %f880;
	add.f32 	%f892, %f891, 0f3F000000;
	max.f32 	%f894, %f1123, %f878;
	min.f32 	%f895, %f894, %f880;
	add.f32 	%f896, %f895, 0f3F000000;
	st.global.v4.f32 	[%r529], {%f882, %f887, %f892, %f896};
	bra.uni 	BB11_400;

BB11_394:
	ld.shared.v4.f32 	{%f1116, %f1117, %f1118, %f1119}, [%r521];
	@%p5 bra 	BB11_395;
	bra.uni 	BB11_399;

BB11_395:
	setp.lt.f32 	%p352, %f216, 0f00000000;
	selp.f32 	%f228, 0fBF800000, 0f3F800000, %p352;
	mul.f32 	%f897, %f228, %f216;
	setp.ltu.f32 	%p353, %f897, 0f00000000;
	@%p353 bra 	BB11_397;

	rcp.approx.f32 	%f1115, %f216;
	bra.uni 	BB11_398;

BB11_397:
	mul.f32 	%f1115, %f228, 0f7F800000;

BB11_398:
	mul.f32 	%f1116, %f1116, %f1115;
	mul.f32 	%f1117, %f1117, %f1115;
	mul.f32 	%f1118, %f1118, %f1115;
	mul.f32 	%f1119, %f1119, %f1115;

BB11_399:
	mov.f32 	%f902, 0f00000000;
	max.f32 	%f903, %f1116, %f902;
	mov.f32 	%f904, 0f477FFF00;
	min.f32 	%f905, %f903, %f904;
	add.f32 	%f906, %f905, 0f3F000000;
	max.f32 	%f908, %f1117, %f902;
	min.f32 	%f909, %f908, %f904;
	add.f32 	%f910, %f909, 0f3F000000;
	max.f32 	%f912, %f1118, %f902;
	min.f32 	%f913, %f912, %f904;
	add.f32 	%f914, %f913, 0f3F000000;
	max.f32 	%f916, %f1119, %f902;
	min.f32 	%f917, %f916, %f904;
	add.f32 	%f918, %f917, 0f3F000000;
	st.global.v4.f32 	[%r529], {%f906, %f910, %f914, %f918};

BB11_400:
	add.s32 	%r1710, %r1710, 1;
	setp.lt.u32 	%p354, %r1710, %r26;
	@%p354 bra 	BB11_8;

BB11_401:
	ret;
}

.entry ResizeHorizontalFilterSinc(
	.param .u32 .ptr .global .align 16 ResizeHorizontalFilterSinc_param_0,
	.param .u32 ResizeHorizontalFilterSinc_param_1,
	.param .u32 ResizeHorizontalFilterSinc_param_2,
	.param .u32 ResizeHorizontalFilterSinc_param_3,
	.param .f32 ResizeHorizontalFilterSinc_param_4,
	.param .u32 .ptr .global .align 16 ResizeHorizontalFilterSinc_param_5,
	.param .u32 ResizeHorizontalFilterSinc_param_6,
	.param .u32 ResizeHorizontalFilterSinc_param_7,
	.param .u32 ResizeHorizontalFilterSinc_param_8,
	.param .u32 ResizeHorizontalFilterSinc_param_9,
	.param .u32 .ptr .global .align 4 ResizeHorizontalFilterSinc_param_10,
	.param .f32 ResizeHorizontalFilterSinc_param_11,
	.param .f32 ResizeHorizontalFilterSinc_param_12,
	.param .f32 ResizeHorizontalFilterSinc_param_13,
	.param .f32 ResizeHorizontalFilterSinc_param_14,
	.param .u32 .ptr .shared .align 16 ResizeHorizontalFilterSinc_param_15,
	.param .u32 ResizeHorizontalFilterSinc_param_16,
	.param .u32 ResizeHorizontalFilterSinc_param_17,
	.param .u32 ResizeHorizontalFilterSinc_param_18,
	.param .u32 .ptr .shared .align 16 ResizeHorizontalFilterSinc_param_19,
	.param .u32 .ptr .shared .align 4 ResizeHorizontalFilterSinc_param_20,
	.param .u32 .ptr .shared .align 4 ResizeHorizontalFilterSinc_param_21
)
.reqntid 256, 1, 1
{
	.reg .f32 	%f<480>;
	.reg .pred 	%p<66>;
	.reg .s32 	%r<189>;


	ld.param.f32 	%f1, [ResizeHorizontalFilterSinc_param_4];
	ld.param.u32 	%r5, [ResizeHorizontalFilterSinc_param_6];
	ld.param.f32 	%f86, [ResizeHorizontalFilterSinc_param_12];
	ld.param.u32 	%r8, [ResizeHorizontalFilterSinc_param_17];
	// inline asm
	mov.u32 	%r71, %envreg0;
	// inline asm
	// inline asm
	mov.u32 	%r72, %ctaid.x;
	// inline asm
	add.s32 	%r76, %r72, %r71;
	mul.lo.s32 	%r15, %r76, %r8;
	mad.lo.s32 	%r74, %r76, %r8, %r8;
	// inline asm
	min.u32 	%r73, %r74, %r5;
	// inline asm
	rcp.approx.f32 	%f87, %f1;
	mov.f32 	%f88, 0f3F800000;
	add.f32 	%f89, %f87, 0f00000000;
	max.f32 	%f5, %f89, %f88;
	mul.f32 	%f90, %f5, %f86;
	mov.f32 	%f91, 0f3F000000;
	max.f32 	%f6, %f90, %f91;
	setp.lt.f32 	%p7, %f5, 0f00000000;
	selp.f32 	%f7, 0fBF800000, 0f3F800000, %p7;
	mul.f32 	%f92, %f7, %f5;
	setp.ltu.f32 	%p8, %f92, 0f00000000;
	@%p8 bra 	BB12_2;

	rcp.approx.f32 	%f449, %f5;
	bra.uni 	BB12_3;

BB12_2:
	mul.f32 	%f449, %f7, 0f7F800000;

BB12_3:
	cvt.rn.f32.u32 	%f93, %r15;
	add.f32 	%f94, %f93, 0f3F000000;
	ld.param.f32 	%f442, [ResizeHorizontalFilterSinc_param_4];
	div.full.f32 	%f95, %f94, %f442;
	add.f32 	%f96, %f95, 0f00000000;
	sub.f32 	%f97, %f96, %f6;
	add.f32 	%f98, %f97, 0f3F000000;
	cvt.rzi.s32.f32 	%r78, %f98;
	mov.u32 	%r79, 0;
	// inline asm
	max.s32 	%r77, %r78, %r79;
	// inline asm
	ld.param.u32 	%r171, [ResizeHorizontalFilterSinc_param_16];
	add.s32 	%r81, %r77, %r171;
	ld.param.u32 	%r160, [ResizeHorizontalFilterSinc_param_1];
	// inline asm
	min.s32 	%r80, %r81, %r160;
	// inline asm
	// inline asm
	mov.u32 	%r83, %envreg4;
	// inline asm
	// inline asm
	mov.u32 	%r84, %ntid.y;
	// inline asm
	// inline asm
	mov.u32 	%r85, %ctaid.y;
	// inline asm
	// inline asm
	mov.u32 	%r86, %tid.y;
	// inline asm
	add.s32 	%r89, %r86, %r83;
	mad.lo.s32 	%r18, %r85, %r84, %r89;
	mul.lo.s32 	%r19, %r18, %r160;
	sub.s32 	%r20, %r80, %r77;
	// inline asm
	mov.u32 	%r87, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r88, %tid.x;
	// inline asm
	setp.ge.u32 	%p9, %r88, %r20;
	mov.u32 	%r182, %r88;
	@%p9 bra 	BB12_6;

	add.s32 	%r23, %r19, %r77;

BB12_5:
	add.s32 	%r90, %r23, %r182;
	shl.b32 	%r91, %r90, 4;
	ld.param.u32 	%r159, [ResizeHorizontalFilterSinc_param_0];
	add.s32 	%r92, %r159, %r91;
	shl.b32 	%r93, %r182, 4;
	ld.param.u32 	%r170, [ResizeHorizontalFilterSinc_param_15];
	add.s32 	%r94, %r170, %r93;
	ld.global.v4.f32 	{%f437, %f438, %f439, %f440}, [%r92];
	st.shared.v4.f32 	[%r94], {%f437, %f438, %f439, %f440};
	add.s32 	%r182, %r182, %r87;
	setp.lt.u32 	%p10, %r182, %r20;
	@%p10 bra 	BB12_5;

BB12_6:
	membar.gl;
	bar.sync 	0;
	ld.param.u32 	%r173, [ResizeHorizontalFilterSinc_param_18];
	add.s32 	%r95, %r173, %r73;
	add.s32 	%r96, %r95, -1;
	sub.s32 	%r97, %r96, %r15;
	div.u32 	%r26, %r97, %r173;
	setp.eq.s32 	%p11, %r26, 0;
	@%p11 bra 	BB12_89;

	ld.param.u32 	%r167, [ResizeHorizontalFilterSinc_param_6];
	mul.lo.s32 	%r27, %r18, %r167;
	ld.param.u32 	%r161, [ResizeHorizontalFilterSinc_param_1];
	cvt.rn.f32.u32 	%f11, %r161;
	mov.f32 	%f12, 0fFF800000;
	neg.s32 	%r28, %r77;
	mov.u32 	%r184, 0;
	ld.param.u32 	%r172, [ResizeHorizontalFilterSinc_param_17];
	mul.lo.s32 	%r100, %r172, %r76;
	neg.s32 	%r183, %r100;

BB12_8:
	ld.param.u32 	%r175, [ResizeHorizontalFilterSinc_param_18];
	mad.lo.s32 	%r32, %r184, %r175, %r15;
	add.s32 	%r102, %r32, %r175;
	// inline asm
	min.u32 	%r101, %r102, %r73;
	// inline asm
	sub.s32 	%r34, %r101, %r32;
	// inline asm
	mov.u32 	%r104, %tid.x;
	// inline asm
	// inline asm
	mov.u32 	%r105, %ntid.x;
	// inline asm
	div.u32 	%r37, %r105, %r34;
	// inline asm
	mov.u32 	%r106, %ntid.x;
	// inline asm
	div.u32 	%r107, %r106, %r34;
	div.u32 	%r108, %r104, %r107;
	setp.lt.u32 	%p12, %r108, %r34;
	selp.b32 	%r38, %r108, -1, %p12;
	setp.eq.s32 	%p1, %r38, -1;
	@%p1 bra 	BB12_60;

	add.s32 	%r109, %r38, %r32;
	cvt.rn.f32.s32 	%f99, %r109;
	add.f32 	%f100, %f99, 0f3F000000;
	ld.param.f32 	%f441, [ResizeHorizontalFilterSinc_param_4];
	div.full.f32 	%f101, %f100, %f441;
	add.f32 	%f13, %f101, 0f00000000;
	mov.f32 	%f462, 0f00000000;
	sub.f32 	%f103, %f13, %f6;
	add.f32 	%f104, %f103, 0f3F000000;
	max.f32 	%f105, %f104, %f462;
	cvt.rzi.u32.f32 	%r39, %f105;
	add.f32 	%f106, %f13, %f6;
	add.f32 	%f107, %f106, 0f3F000000;
	min.f32 	%f108, %f107, %f11;
	cvt.rzi.u32.f32 	%r40, %f108;
	sub.s32 	%r41, %r40, %r39;
	div.u32 	%r110, %r41, %r37;
	mul.lo.s32 	%r111, %r110, %r37;
	setp.ne.s32 	%p2, %r111, %r41;
	selp.u32 	%r112, 1, 0, %p2;
	add.s32 	%r42, %r112, %r110;
	rem.u32 	%r43, %r104, %r37;
	mul.lo.s32 	%r187, %r42, %r43;
	setp.ge.u32 	%p13, %r187, %r41;
	@%p13 bra 	BB12_60;

	add.s32 	%r114, %r187, %r42;
	// inline asm
	min.u32 	%r113, %r114, %r41;
	// inline asm
	setp.lt.u32 	%p3, %r187, %r113;
	ld.param.u32 	%r165, [ResizeHorizontalFilterSinc_param_3];
	setp.eq.s32 	%p14, %r165, 0;
	@%p14 bra 	BB12_35;

	@!%p3 bra 	BB12_60;

	add.s32 	%r116, %r28, %r39;
	add.s32 	%r117, %r101, %r183;
	div.u32 	%r118, %r105, %r117;
	div.u32 	%r120, %r41, %r118;
	add.s32 	%r122, %r120, %r112;
	mad.lo.s32 	%r123, %r43, %r122, %r116;
	shl.b32 	%r124, %r123, 4;
	ld.param.u32 	%r169, [ResizeHorizontalFilterSinc_param_15];
	add.s32 	%r185, %r169, %r124;
	mov.f32 	%f476, %f462;
	mov.f32 	%f477, %f462;
	mov.f32 	%f478, %f462;
	mov.f32 	%f479, %f462;
	mov.f32 	%f463, %f462;

BB12_13:
	ld.shared.v4.f32 	{%f425, %f426, %f427, %f428}, [%r185];
	add.s32 	%r125, %r39, %r187;
	cvt.rn.f32.u32 	%f113, %r125;
	sub.f32 	%f114, %f113, %f13;
	add.f32 	%f115, %f114, 0f3F000000;
	mul.f32 	%f116, %f449, %f115;
	ld.param.f32 	%f448, [ResizeHorizontalFilterSinc_param_14];
	div.full.f32 	%f112, %f116, %f448;
	// inline asm
	abs.f32 	%f111, %f112;
	// inline asm
	ld.param.f32 	%f446, [ResizeHorizontalFilterSinc_param_13];
	setp.lt.f32 	%p15, %f446, 0f00000000;
	@%p15 bra 	BB12_23;

	ld.param.f32 	%f443, [ResizeHorizontalFilterSinc_param_11];
	mul.f32 	%f17, %f111, %f443;
	setp.eq.f32 	%p16, %f17, 0f00000000;
	@%p16 bra 	BB12_23;

	mul.f32 	%f18, %f17, 0f40490FDC;
	setp.eq.f32 	%p17, %f17, 0f7F800000;
	@%p17 bra 	BB12_21;

	setp.eq.f32 	%p18, %f17, %f12;
	or.pred  	%p20, %p18, %p16;
	@%p20 bra 	BB12_21;

	mov.f32 	%f121, 0f40000000;
	mul.rn.f32 	%f118, %f121, %f17;
	// inline asm
	cvt.rni.f32.f32 	%f117, %f118;
	// inline asm
	cvt.rzi.s32.f32 	%r126, %f117;
	neg.f32 	%f122, %f117;
	mul.rn.f32 	%f124, %f122, %f91;
	add.f32 	%f125, %f124, %f17;
	mov.f32 	%f126, 0f40490FDB;
	mul.rn.f32 	%f127, %f125, %f126;
	// inline asm
	abs.f32 	%f119, %f17;
	// inline asm
	setp.gt.f32 	%p21, %f119, 0f4B800000;
	selp.f32 	%f19, 0f00000000, %f127, %p21;
	selp.b32 	%r49, 0, %r126, %p21;
	and.b32  	%r127, %r49, 1;
	setp.eq.s32 	%p22, %r127, 0;
	mul.rn.f32 	%f20, %f19, %f19;
	@%p22 bra 	BB12_19;

	mov.f32 	%f128, 0f37CCF5CE;
	mul.rn.f32 	%f129, %f128, %f20;
	add.f32 	%f130, %f129, 0fBAB6061A;
	mul.rn.f32 	%f131, %f130, %f20;
	add.f32 	%f132, %f131, 0f3D2AAAA5;
	mul.rn.f32 	%f133, %f132, %f20;
	add.f32 	%f134, %f133, 0fBF000000;
	mul.rn.f32 	%f135, %f134, %f20;
	add.f32 	%f450, %f135, 0f3F800000;
	bra.uni 	BB12_20;

BB12_19:
	mov.f32 	%f136, 0fB94CA1F9;
	mul.rn.f32 	%f137, %f136, %f20;
	add.f32 	%f138, %f137, 0f3C08839E;
	mul.rn.f32 	%f139, %f138, %f20;
	add.f32 	%f140, %f139, 0fBE2AAAA3;
	mul.rn.f32 	%f141, %f140, %f20;
	mul.rn.f32 	%f142, %f141, %f19;
	add.f32 	%f450, %f142, %f19;

BB12_20:
	and.b32  	%r128, %r49, 2;
	setp.eq.s32 	%p23, %r128, 0;
	neg.f32 	%f143, %f450;
	selp.f32 	%f451, %f450, %f143, %p23;
	bra.uni 	BB12_22;

BB12_21:
	mov.f32 	%f144, 0f00000000;
	mul.rn.f32 	%f451, %f17, %f144;

BB12_22:
	div.full.f32 	%f452, %f451, %f18;
	bra.uni 	BB12_24;

BB12_23:
	mov.f32 	%f452, 0f3F800000;

BB12_24:
	setp.neu.f32 	%p24, %f111, 0f00000000;
	@%p24 bra 	BB12_26;

	mov.f32 	%f455, %f88;
	bra.uni 	BB12_34;

BB12_26:
	mul.f32 	%f29, %f111, 0f40490FDC;
	setp.eq.f32 	%p25, %f111, 0f7F800000;
	@%p25 bra 	BB12_32;

	setp.eq.f32 	%p26, %f111, %f12;
	setp.eq.f32 	%p27, %f111, 0f00000000;
	or.pred  	%p28, %p26, %p27;
	@%p28 bra 	BB12_32;

	mov.f32 	%f151, 0f40000000;
	mul.rn.f32 	%f148, %f151, %f111;
	// inline asm
	cvt.rni.f32.f32 	%f147, %f148;
	// inline asm
	cvt.rzi.s32.f32 	%r129, %f147;
	neg.f32 	%f152, %f147;
	mul.rn.f32 	%f154, %f152, %f91;
	add.f32 	%f155, %f154, %f111;
	mov.f32 	%f156, 0f40490FDB;
	mul.rn.f32 	%f157, %f155, %f156;
	// inline asm
	abs.f32 	%f149, %f111;
	// inline asm
	setp.gt.f32 	%p29, %f149, 0f4B800000;
	selp.f32 	%f30, 0f00000000, %f157, %p29;
	selp.b32 	%r50, 0, %r129, %p29;
	and.b32  	%r130, %r50, 1;
	setp.eq.s32 	%p30, %r130, 0;
	mul.rn.f32 	%f31, %f30, %f30;
	@%p30 bra 	BB12_30;

	mov.f32 	%f158, 0f37CCF5CE;
	mul.rn.f32 	%f159, %f158, %f31;
	add.f32 	%f160, %f159, 0fBAB6061A;
	mul.rn.f32 	%f161, %f160, %f31;
	add.f32 	%f162, %f161, 0f3D2AAAA5;
	mul.rn.f32 	%f163, %f162, %f31;
	add.f32 	%f164, %f163, 0fBF000000;
	mul.rn.f32 	%f165, %f164, %f31;
	add.f32 	%f453, %f165, 0f3F800000;
	bra.uni 	BB12_31;

BB12_30:
	mov.f32 	%f166, 0fB94CA1F9;
	mul.rn.f32 	%f167, %f166, %f31;
	add.f32 	%f168, %f167, 0f3C08839E;
	mul.rn.f32 	%f169, %f168, %f31;
	add.f32 	%f170, %f169, 0fBE2AAAA3;
	mul.rn.f32 	%f171, %f170, %f31;
	mul.rn.f32 	%f172, %f171, %f30;
	add.f32 	%f453, %f172, %f30;

BB12_31:
	and.b32  	%r131, %r50, 2;
	setp.eq.s32 	%p31, %r131, 0;
	neg.f32 	%f173, %f453;
	selp.f32 	%f454, %f453, %f173, %p31;
	bra.uni 	BB12_33;

BB12_32:
	mov.f32 	%f174, 0f00000000;
	mul.rn.f32 	%f454, %f111, %f174;

BB12_33:
	div.full.f32 	%f38, %f454, %f29;
	mov.f32 	%f455, %f38;

BB12_34:
	mov.f32 	%f39, %f455;
	mul.f32 	%f175, %f452, %f39;
	mul.f32 	%f176, %f175, 0f377BA882;
	mov.f32 	%f178, 0f477FFF00;
	sub.f32 	%f179, %f178, %f428;
	mul.f32 	%f180, %f176, %f179;
	mad.f32 	%f183, %f180, %f425, %f476;
	mad.f32 	%f186, %f180, %f426, %f477;
	mad.f32 	%f189, %f180, %f427, %f478;
	mad.f32 	%f191, %f175, %f428, %f479;
	mov.f32 	%f476, %f183;
	mov.f32 	%f477, %f186;
	mov.f32 	%f478, %f189;
	mov.f32 	%f479, %f191;
	mad.f32 	%f462, %f452, %f39, %f462;
	mad.f32 	%f463, %f176, %f179, %f463;
	add.s32 	%r185, %r185, 16;
	add.s32 	%r187, %r187, 1;
	setp.lt.u32 	%p32, %r187, %r113;
	@%p32 bra 	BB12_13;
	bra.uni 	BB12_61;

BB12_35:
	@!%p3 bra 	BB12_60;

	add.s32 	%r132, %r28, %r39;
	add.s32 	%r133, %r101, %r183;
	div.u32 	%r134, %r105, %r133;
	div.u32 	%r136, %r41, %r134;
	add.s32 	%r138, %r136, %r112;
	mad.lo.s32 	%r139, %r43, %r138, %r132;
	shl.b32 	%r140, %r139, 4;
	ld.param.u32 	%r168, [ResizeHorizontalFilterSinc_param_15];
	add.s32 	%r186, %r168, %r140;
	ld.param.f32 	%f445, [ResizeHorizontalFilterSinc_param_13];
	setp.lt.f32 	%p4, %f445, 0f00000000;
	mov.f32 	%f462, 0f00000000;
	mov.f32 	%f476, %f462;
	mov.f32 	%f477, %f462;
	mov.f32 	%f478, %f462;
	mov.f32 	%f479, %f462;

BB12_37:
	ld.shared.v4.f32 	{%f413, %f414, %f415, %f416}, [%r186];
	add.s32 	%r141, %r39, %r187;
	cvt.rn.f32.u32 	%f195, %r141;
	sub.f32 	%f196, %f195, %f13;
	add.f32 	%f197, %f196, 0f3F000000;
	mul.f32 	%f198, %f449, %f197;
	ld.param.f32 	%f447, [ResizeHorizontalFilterSinc_param_14];
	div.full.f32 	%f194, %f198, %f447;
	// inline asm
	abs.f32 	%f193, %f194;
	// inline asm
	@%p4 bra 	BB12_47;

	ld.param.f32 	%f444, [ResizeHorizontalFilterSinc_param_11];
	mul.f32 	%f44, %f193, %f444;
	setp.eq.f32 	%p33, %f44, 0f00000000;
	@%p33 bra 	BB12_47;

	mul.f32 	%f45, %f44, 0f40490FDC;
	setp.eq.f32 	%p34, %f44, 0f7F800000;
	@%p34 bra 	BB12_45;

	setp.eq.f32 	%p35, %f44, %f12;
	or.pred  	%p37, %p35, %p33;
	@%p37 bra 	BB12_45;

	mov.f32 	%f203, 0f40000000;
	mul.rn.f32 	%f200, %f203, %f44;
	// inline asm
	cvt.rni.f32.f32 	%f199, %f200;
	// inline asm
	cvt.rzi.s32.f32 	%r142, %f199;
	neg.f32 	%f204, %f199;
	mul.rn.f32 	%f206, %f204, %f91;
	add.f32 	%f207, %f206, %f44;
	mov.f32 	%f208, 0f40490FDB;
	mul.rn.f32 	%f209, %f207, %f208;
	// inline asm
	abs.f32 	%f201, %f44;
	// inline asm
	setp.gt.f32 	%p38, %f201, 0f4B800000;
	selp.f32 	%f46, 0f00000000, %f209, %p38;
	selp.b32 	%r56, 0, %r142, %p38;
	and.b32  	%r143, %r56, 1;
	setp.eq.s32 	%p39, %r143, 0;
	mul.rn.f32 	%f47, %f46, %f46;
	@%p39 bra 	BB12_43;

	mov.f32 	%f210, 0f37CCF5CE;
	mul.rn.f32 	%f211, %f210, %f47;
	add.f32 	%f212, %f211, 0fBAB6061A;
	mul.rn.f32 	%f213, %f212, %f47;
	add.f32 	%f214, %f213, 0f3D2AAAA5;
	mul.rn.f32 	%f215, %f214, %f47;
	add.f32 	%f216, %f215, 0fBF000000;
	mul.rn.f32 	%f217, %f216, %f47;
	add.f32 	%f456, %f217, 0f3F800000;
	bra.uni 	BB12_44;

BB12_43:
	mov.f32 	%f218, 0fB94CA1F9;
	mul.rn.f32 	%f219, %f218, %f47;
	add.f32 	%f220, %f219, 0f3C08839E;
	mul.rn.f32 	%f221, %f220, %f47;
	add.f32 	%f222, %f221, 0fBE2AAAA3;
	mul.rn.f32 	%f223, %f222, %f47;
	mul.rn.f32 	%f224, %f223, %f46;
	add.f32 	%f456, %f224, %f46;

BB12_44:
	and.b32  	%r144, %r56, 2;
	setp.eq.s32 	%p40, %r144, 0;
	neg.f32 	%f225, %f456;
	selp.f32 	%f457, %f456, %f225, %p40;
	bra.uni 	BB12_46;

BB12_45:
	mov.f32 	%f226, 0f00000000;
	mul.rn.f32 	%f457, %f44, %f226;

BB12_46:
	div.full.f32 	%f458, %f457, %f45;
	bra.uni 	BB12_48;

BB12_47:
	mov.f32 	%f458, 0f3F800000;

BB12_48:
	setp.neu.f32 	%p41, %f193, 0f00000000;
	@%p41 bra 	BB12_50;

	mov.f32 	%f461, 0f3F800000;
	bra.uni 	BB12_58;

BB12_50:
	mul.f32 	%f56, %f193, 0f40490FDC;
	setp.eq.f32 	%p42, %f193, 0f7F800000;
	@%p42 bra 	BB12_56;

	setp.eq.f32 	%p43, %f193, %f12;
	setp.eq.f32 	%p44, %f193, 0f00000000;
	or.pred  	%p45, %p43, %p44;
	@%p45 bra 	BB12_56;

	mov.f32 	%f233, 0f40000000;
	mul.rn.f32 	%f230, %f233, %f193;
	// inline asm
	cvt.rni.f32.f32 	%f229, %f230;
	// inline asm
	cvt.rzi.s32.f32 	%r145, %f229;
	neg.f32 	%f234, %f229;
	mul.rn.f32 	%f236, %f234, %f91;
	add.f32 	%f237, %f236, %f193;
	mov.f32 	%f238, 0f40490FDB;
	mul.rn.f32 	%f239, %f237, %f238;
	// inline asm
	abs.f32 	%f231, %f193;
	// inline asm
	setp.gt.f32 	%p46, %f231, 0f4B800000;
	selp.f32 	%f57, 0f00000000, %f239, %p46;
	selp.b32 	%r57, 0, %r145, %p46;
	and.b32  	%r146, %r57, 1;
	setp.eq.s32 	%p47, %r146, 0;
	mul.rn.f32 	%f58, %f57, %f57;
	@%p47 bra 	BB12_54;

	mov.f32 	%f240, 0f37CCF5CE;
	mul.rn.f32 	%f241, %f240, %f58;
	add.f32 	%f242, %f241, 0fBAB6061A;
	mul.rn.f32 	%f243, %f242, %f58;
	add.f32 	%f244, %f243, 0f3D2AAAA5;
	mul.rn.f32 	%f245, %f244, %f58;
	add.f32 	%f246, %f245, 0fBF000000;
	mul.rn.f32 	%f247, %f246, %f58;
	add.f32 	%f459, %f247, 0f3F800000;
	bra.uni 	BB12_55;

BB12_54:
	mov.f32 	%f248, 0fB94CA1F9;
	mul.rn.f32 	%f249, %f248, %f58;
	add.f32 	%f250, %f249, 0f3C08839E;
	mul.rn.f32 	%f251, %f250, %f58;
	add.f32 	%f252, %f251, 0fBE2AAAA3;
	mul.rn.f32 	%f253, %f252, %f58;
	mul.rn.f32 	%f254, %f253, %f57;
	add.f32 	%f459, %f254, %f57;

BB12_55:
	and.b32  	%r147, %r57, 2;
	setp.eq.s32 	%p48, %r147, 0;
	neg.f32 	%f255, %f459;
	selp.f32 	%f460, %f459, %f255, %p48;
	bra.uni 	BB12_57;

BB12_56:
	mov.f32 	%f256, 0f00000000;
	mul.rn.f32 	%f460, %f193, %f256;

BB12_57:
	div.full.f32 	%f461, %f460, %f56;

BB12_58:
	mul.f32 	%f257, %f458, %f461;
	mad.f32 	%f476, %f257, %f413, %f476;
	mad.f32 	%f477, %f257, %f414, %f477;
	mad.f32 	%f478, %f257, %f415, %f478;
	mad.f32 	%f479, %f257, %f416, %f479;
	mad.f32 	%f462, %f458, %f461, %f462;
	add.s32 	%r186, %r186, 16;
	add.s32 	%r187, %r187, 1;
	setp.lt.u32 	%p49, %r187, %r113;
	@%p49 bra 	BB12_37;

	mov.f32 	%f463, 0f00000000;
	bra.uni 	BB12_61;

BB12_60:
	mov.f32 	%f463, 0f00000000;
	mov.f32 	%f476, %f463;
	mov.f32 	%f477, %f463;
	mov.f32 	%f478, %f463;
	mov.f32 	%f479, %f463;
	mov.f32 	%f462, %f463;

BB12_61:
	shl.b32 	%r148, %r104, 4;
	ld.param.u32 	%r177, [ResizeHorizontalFilterSinc_param_19];
	add.s32 	%r60, %r177, %r148;
	shl.b32 	%r149, %r104, 2;
	ld.param.u32 	%r179, [ResizeHorizontalFilterSinc_param_20];
	add.s32 	%r61, %r179, %r149;
	ld.param.u32 	%r181, [ResizeHorizontalFilterSinc_param_21];
	add.s32 	%r62, %r181, %r149;
	setp.lt.u32 	%p5, %r104, %r34;
	setp.ge.u32 	%p50, %r104, %r34;
	@%p50 bra 	BB12_64;

	mov.f32 	%f264, 0f00000000;
	st.shared.v4.f32 	[%r60], {%f264, %f264, %f264, %f264};
	mov.u32 	%r150, 0;
	st.shared.u32 	[%r61], %r150;
	ld.param.u32 	%r164, [ResizeHorizontalFilterSinc_param_3];
	setp.eq.s32 	%p51, %r164, 0;
	@%p51 bra 	BB12_64;

	st.shared.u32 	[%r62], %r150;

BB12_64:
	bar.sync 	0;
	setp.eq.s32 	%p52, %r37, 0;
	@%p52 bra 	BB12_71;

	shl.b32 	%r153, %r38, 4;
	ld.param.u32 	%r176, [ResizeHorizontalFilterSinc_param_19];
	add.s32 	%r63, %r176, %r153;
	shl.b32 	%r154, %r38, 2;
	ld.param.u32 	%r178, [ResizeHorizontalFilterSinc_param_20];
	add.s32 	%r64, %r178, %r154;
	ld.param.u32 	%r180, [ResizeHorizontalFilterSinc_param_21];
	add.s32 	%r65, %r180, %r154;
	mov.u32 	%r188, 0;

BB12_66:
	@%p1 bra 	BB12_70;

	rem.u32 	%r155, %r104, %r37;
	setp.ne.s32 	%p53, %r188, %r155;
	@%p53 bra 	BB12_70;

	ld.shared.v4.f32 	{%f373, %f374, %f375, %f376}, [%r63];
	add.f32 	%f377, %f373, %f476;
	add.f32 	%f378, %f374, %f477;
	add.f32 	%f379, %f375, %f478;
	add.f32 	%f380, %f376, %f479;
	st.shared.v4.f32 	[%r63], {%f377, %f378, %f379, %f380};
	ld.shared.f32 	%f265, [%r64];
	add.f32 	%f266, %f265, %f462;
	st.shared.f32 	[%r64], %f266;
	ld.param.u32 	%r163, [ResizeHorizontalFilterSinc_param_3];
	setp.eq.s32 	%p54, %r163, 0;
	@%p54 bra 	BB12_70;

	ld.shared.f32 	%f267, [%r65];
	add.f32 	%f268, %f267, %f463;
	st.shared.f32 	[%r65], %f268;

BB12_70:
	bar.sync 	0;
	add.s32 	%r188, %r188, 1;
	setp.lt.u32 	%p55, %r188, %r37;
	@%p55 bra 	BB12_66;

BB12_71:
	@!%p5 bra 	BB12_88;

	ld.shared.f32 	%f70, [%r61];
	setp.neu.f32 	%p56, %f70, 0f00000000;
	setp.neu.f32 	%p57, %f70, 0f3F800000;
	and.pred  	%p6, %p56, %p57;
	add.s32 	%r156, %r32, %r27;
	add.s32 	%r157, %r156, %r104;
	shl.b32 	%r158, %r157, 4;
	ld.param.u32 	%r166, [ResizeHorizontalFilterSinc_param_5];
	add.s32 	%r68, %r166, %r158;
	ld.param.u32 	%r162, [ResizeHorizontalFilterSinc_param_3];
	setp.eq.s32 	%p58, %r162, 0;
	@%p58 bra 	BB12_82;

	ld.shared.f32 	%f465, [%r62];
	ld.shared.v4.f32 	{%f472, %f473, %f474, %f475}, [%r60];
	@%p6 bra 	BB12_74;
	bra.uni 	BB12_78;

BB12_74:
	setp.lt.f32 	%p59, %f70, 0f00000000;
	selp.f32 	%f72, 0fBF800000, 0f3F800000, %p59;
	mul.f32 	%f269, %f72, %f70;
	setp.ltu.f32 	%p60, %f269, 0f00000000;
	@%p60 bra 	BB12_76;

	rcp.approx.f32 	%f464, %f70;
	bra.uni 	BB12_77;

BB12_76:
	mul.f32 	%f464, %f72, 0f7F800000;

BB12_77:
	mul.f32 	%f472, %f472, %f464;
	mul.f32 	%f473, %f473, %f464;
	mul.f32 	%f474, %f474, %f464;
	mul.f32 	%f475, %f475, %f464;
	mul.f32 	%f465, %f465, %f464;

BB12_78:
	setp.lt.f32 	%p61, %f465, 0f00000000;
	selp.f32 	%f78, 0fBF800000, 0f3F800000, %p61;
	mul.f32 	%f273, %f78, %f465;
	setp.ltu.f32 	%p62, %f273, 0f00000000;
	@%p62 bra 	BB12_80;

	rcp.approx.f32 	%f466, %f465;
	bra.uni 	BB12_81;

BB12_80:
	mul.f32 	%f466, %f78, 0f7F800000;

BB12_81:
	mul.f32 	%f275, %f466, %f472;
	mov.f32 	%f276, 0f00000000;
	max.f32 	%f277, %f275, %f276;
	mov.f32 	%f278, 0f477FFF00;
	min.f32 	%f279, %f277, %f278;
	add.f32 	%f280, %f279, 0f3F000000;
	mul.f32 	%f282, %f466, %f473;
	max.f32 	%f283, %f282, %f276;
	min.f32 	%f284, %f283, %f278;
	add.f32 	%f285, %f284, 0f3F000000;
	mul.f32 	%f287, %f466, %f474;
	max.f32 	%f288, %f287, %f276;
	min.f32 	%f289, %f288, %f278;
	add.f32 	%f290, %f289, 0f3F000000;
	max.f32 	%f292, %f475, %f276;
	min.f32 	%f293, %f292, %f278;
	add.f32 	%f294, %f293, 0f3F000000;
	st.global.v4.f32 	[%r68], {%f280, %f285, %f290, %f294};
	bra.uni 	BB12_88;

BB12_82:
	ld.shared.v4.f32 	{%f468, %f469, %f470, %f471}, [%r60];
	@%p6 bra 	BB12_83;
	bra.uni 	BB12_87;

BB12_83:
	setp.lt.f32 	%p63, %f70, 0f00000000;
	selp.f32 	%f82, 0fBF800000, 0f3F800000, %p63;
	mul.f32 	%f295, %f82, %f70;
	setp.ltu.f32 	%p64, %f295, 0f00000000;
	@%p64 bra 	BB12_85;

	rcp.approx.f32 	%f467, %f70;
	bra.uni 	BB12_86;

BB12_85:
	mul.f32 	%f467, %f82, 0f7F800000;

BB12_86:
	mul.f32 	%f468, %f468, %f467;
	mul.f32 	%f469, %f469, %f467;
	mul.f32 	%f470, %f470, %f467;
	mul.f32 	%f471, %f471, %f467;

BB12_87:
	mov.f32 	%f300, 0f00000000;
	max.f32 	%f301, %f468, %f300;
	mov.f32 	%f302, 0f477FFF00;
	min.f32 	%f303, %f301, %f302;
	add.f32 	%f304, %f303, 0f3F000000;
	max.f32 	%f306, %f469, %f300;
	min.f32 	%f307, %f306, %f302;
	add.f32 	%f308, %f307, 0f3F000000;
	max.f32 	%f310, %f470, %f300;
	min.f32 	%f311, %f310, %f302;
	add.f32 	%f312, %f311, 0f3F000000;
	max.f32 	%f314, %f471, %f300;
	min.f32 	%f315, %f314, %f302;
	add.f32 	%f316, %f315, 0f3F000000;
	st.global.v4.f32 	[%r68], {%f304, %f308, %f312, %f316};

BB12_88:
	add.s32 	%r184, %r184, 1;
	setp.lt.u32 	%p65, %r184, %r26;
	ld.param.u32 	%r174, [ResizeHorizontalFilterSinc_param_18];
	sub.s32 	%r183, %r183, %r174;
	@%p65 bra 	BB12_8;

BB12_89:
	ret;
}

.entry ResizeVerticalFilter(
	.param .u32 .ptr .global .align 16 ResizeVerticalFilter_param_0,
	.param .u32 ResizeVerticalFilter_param_1,
	.param .u32 ResizeVerticalFilter_param_2,
	.param .u32 ResizeVerticalFilter_param_3,
	.param .f32 ResizeVerticalFilter_param_4,
	.param .u32 .ptr .global .align 16 ResizeVerticalFilter_param_5,
	.param .u32 ResizeVerticalFilter_param_6,
	.param .u32 ResizeVerticalFilter_param_7,
	.param .u32 ResizeVerticalFilter_param_8,
	.param .u32 ResizeVerticalFilter_param_9,
	.param .u32 .ptr .global .align 4 ResizeVerticalFilter_param_10,
	.param .f32 ResizeVerticalFilter_param_11,
	.param .f32 ResizeVerticalFilter_param_12,
	.param .f32 ResizeVerticalFilter_param_13,
	.param .f32 ResizeVerticalFilter_param_14,
	.param .u32 .ptr .shared .align 16 ResizeVerticalFilter_param_15,
	.param .u32 ResizeVerticalFilter_param_16,
	.param .u32 ResizeVerticalFilter_param_17,
	.param .u32 ResizeVerticalFilter_param_18,
	.param .u32 .ptr .shared .align 16 ResizeVerticalFilter_param_19,
	.param .u32 .ptr .shared .align 4 ResizeVerticalFilter_param_20,
	.param .u32 .ptr .shared .align 4 ResizeVerticalFilter_param_21
)
.reqntid 1, 256, 1
{
	.local .align 4 .b8 	__local_depot13[28];
	.reg .b32 	%SP;
	.reg .f32 	%f<1128>;
	.reg .pred 	%p<355>;
	.reg .s32 	%r<1846>;


	mov.u32 	%SP, __local_depot13;
	ld.param.f32 	%f1, [ResizeVerticalFilter_param_4];
	ld.param.u32 	%r533, [ResizeVerticalFilter_param_7];
	ld.param.f32 	%f232, [ResizeVerticalFilter_param_12];
	ld.param.u32 	%r534, [ResizeVerticalFilter_param_17];
	// inline asm
	mov.u32 	%r529, %envreg1;
	// inline asm
	// inline asm
	mov.u32 	%r530, %ctaid.y;
	// inline asm
	add.s32 	%r535, %r530, %r529;
	mul.lo.s32 	%r16, %r535, %r534;
	mad.lo.s32 	%r532, %r535, %r534, %r534;
	// inline asm
	min.u32 	%r531, %r532, %r533;
	// inline asm
	rcp.approx.f32 	%f233, %f1;
	mov.f32 	%f234, 0f3F800000;
	add.f32 	%f235, %f233, 0f00000000;
	max.f32 	%f5, %f235, %f234;
	mul.f32 	%f236, %f5, %f232;
	mov.f32 	%f237, 0f3F000000;
	max.f32 	%f6, %f236, %f237;
	setp.lt.f32 	%p6, %f5, 0f00000000;
	selp.f32 	%f7, 0fBF800000, 0f3F800000, %p6;
	mul.f32 	%f238, %f7, %f5;
	setp.ltu.f32 	%p7, %f238, 0f00000000;
	@%p7 bra 	BB13_2;

	rcp.approx.f32 	%f1050, %f5;
	bra.uni 	BB13_3;

BB13_2:
	mul.f32 	%f1050, %f7, 0f7F800000;

BB13_3:
	cvt.rn.f32.u32 	%f239, %r16;
	add.f32 	%f240, %f239, 0f3F000000;
	ld.param.f32 	%f1044, [ResizeVerticalFilter_param_4];
	div.full.f32 	%f241, %f240, %f1044;
	add.f32 	%f242, %f241, 0f00000000;
	sub.f32 	%f243, %f242, %f6;
	add.f32 	%f244, %f243, 0f3F000000;
	cvt.rzi.s32.f32 	%r537, %f244;
	mov.u32 	%r538, 0;
	// inline asm
	max.s32 	%r536, %r537, %r538;
	// inline asm
	ld.param.u32 	%r1700, [ResizeVerticalFilter_param_16];
	add.s32 	%r540, %r536, %r1700;
	ld.param.u32 	%r1644, [ResizeVerticalFilter_param_2];
	// inline asm
	min.s32 	%r539, %r540, %r1644;
	// inline asm
	// inline asm
	mov.u32 	%r542, %envreg3;
	// inline asm
	// inline asm
	mov.u32 	%r543, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r544, %ctaid.x;
	// inline asm
	// inline asm
	mov.u32 	%r545, %tid.x;
	// inline asm
	add.s32 	%r548, %r545, %r542;
	mad.lo.s32 	%r19, %r544, %r543, %r548;
	sub.s32 	%r20, %r539, %r536;
	// inline asm
	mov.u32 	%r546, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r547, %tid.x;
	// inline asm
	setp.ge.u32 	%p8, %r547, %r20;
	mov.u32 	%r1709, %r547;
	@%p8 bra 	BB13_5;

BB13_4:
	add.s32 	%r549, %r1709, %r536;
	ld.param.u32 	%r1643, [ResizeVerticalFilter_param_1];
	mad.lo.s32 	%r550, %r549, %r1643, %r19;
	shl.b32 	%r551, %r550, 4;
	ld.param.u32 	%r1642, [ResizeVerticalFilter_param_0];
	add.s32 	%r552, %r1642, %r551;
	shl.b32 	%r553, %r1709, 4;
	ld.param.u32 	%r1699, [ResizeVerticalFilter_param_15];
	add.s32 	%r554, %r1699, %r553;
	ld.global.v4.f32 	{%f1039, %f1040, %f1041, %f1042}, [%r552];
	st.shared.v4.f32 	[%r554], {%f1039, %f1040, %f1041, %f1042};
	add.s32 	%r1709, %r1709, %r546;
	setp.lt.u32 	%p9, %r1709, %r20;
	@%p9 bra 	BB13_4;

BB13_5:
	membar.gl;
	bar.sync 	0;
	ld.param.u32 	%r1701, [ResizeVerticalFilter_param_18];
	add.s32 	%r555, %r1701, %r531;
	add.s32 	%r556, %r555, -1;
	sub.s32 	%r557, %r556, %r16;
	div.u32 	%r25, %r557, %r1701;
	setp.eq.s32 	%p10, %r25, 0;
	@%p10 bra 	BB13_400;

	ld.param.u32 	%r1645, [ResizeVerticalFilter_param_2];
	cvt.rn.f32.u32 	%f11, %r1645;
	ld.param.u32 	%r1688, [ResizeVerticalFilter_param_9];
	setp.eq.s32 	%p11, %r1688, 0;
	mov.u32 	%r1710, 0;
	ld.param.f32 	%f1047, [ResizeVerticalFilter_param_13];
	setp.lt.f32 	%p12, %f1047, 0f00000000;
	or.pred  	%p1, %p12, %p11;
	mov.f32 	%f12, 0f7F800000;
	mov.f32 	%f13, 0fFF800000;
	mov.f32 	%f14, 0f7FFFFFFF;

BB13_7:
	ld.param.u32 	%r1702, [ResizeVerticalFilter_param_18];
	mad.lo.s32 	%r27, %r1710, %r1702, %r16;
	add.s32 	%r560, %r27, %r1702;
	// inline asm
	min.u32 	%r559, %r560, %r531;
	// inline asm
	sub.s32 	%r28, %r559, %r27;
	// inline asm
	mov.u32 	%r562, %tid.y;
	// inline asm
	// inline asm
	mov.u32 	%r563, %ntid.y;
	// inline asm
	div.u32 	%r30, %r563, %r28;
	// inline asm
	mov.u32 	%r564, %ntid.y;
	// inline asm
	div.u32 	%r565, %r564, %r28;
	div.u32 	%r566, %r562, %r565;
	setp.lt.u32 	%p13, %r566, %r28;
	selp.b32 	%r31, %r566, -1, %p13;
	setp.eq.s32 	%p2, %r31, -1;
	@%p2 bra 	BB13_371;

	add.s32 	%r567, %r31, %r27;
	cvt.rn.f32.s32 	%f245, %r567;
	add.f32 	%f246, %f245, 0f3F000000;
	ld.param.f32 	%f1043, [ResizeVerticalFilter_param_4];
	div.full.f32 	%f247, %f246, %f1043;
	add.f32 	%f15, %f247, 0f00000000;
	mov.f32 	%f1110, 0f00000000;
	sub.f32 	%f249, %f15, %f6;
	add.f32 	%f250, %f249, 0f3F000000;
	max.f32 	%f251, %f250, %f1110;
	cvt.rzi.u32.f32 	%r32, %f251;
	add.f32 	%f252, %f15, %f6;
	add.f32 	%f253, %f252, 0f3F000000;
	min.f32 	%f254, %f253, %f11;
	cvt.rzi.u32.f32 	%r568, %f254;
	sub.s32 	%r33, %r568, %r32;
	div.u32 	%r569, %r33, %r30;
	mul.lo.s32 	%r570, %r569, %r30;
	setp.ne.s32 	%p14, %r570, %r33;
	selp.u32 	%r571, 1, 0, %p14;
	add.s32 	%r34, %r571, %r569;
	rem.u32 	%r572, %r562, %r30;
	mul.lo.s32 	%r1777, %r34, %r572;
	setp.ge.u32 	%p15, %r1777, %r33;
	@%p15 bra 	BB13_371;

	add.s32 	%r574, %r1777, %r34;
	// inline asm
	min.u32 	%r573, %r574, %r33;
	// inline asm
	sub.s32 	%r576, %r32, %r536;
	add.s32 	%r1778, %r576, %r1777;
	setp.lt.u32 	%p3, %r1777, %r573;
	add.u32 	%r38, %SP, 0;
	ld.param.u32 	%r1649, [ResizeVerticalFilter_param_3];
	setp.eq.s32 	%p16, %r1649, 0;
	@%p16 bra 	BB13_190;

	@!%p3 bra 	BB13_371;

	mov.f32 	%f1124, %f1110;
	mov.f32 	%f1125, %f1110;
	mov.f32 	%f1126, %f1110;
	mov.f32 	%f1127, %f1110;
	mov.f32 	%f1111, %f1110;

BB13_12:
	shl.b32 	%r577, %r1778, 4;
	ld.param.u32 	%r1698, [ResizeVerticalFilter_param_15];
	add.s32 	%r578, %r1698, %r577;
	ld.shared.v4.f32 	{%f1027, %f1028, %f1029, %f1030}, [%r578];
	add.s32 	%r579, %r1777, %r32;
	cvt.rn.f32.u32 	%f259, %r579;
	sub.f32 	%f260, %f259, %f15;
	add.f32 	%f261, %f260, 0f3F000000;
	mul.f32 	%f262, %f1050, %f261;
	ld.param.f32 	%f1049, [ResizeVerticalFilter_param_14];
	div.full.f32 	%f258, %f262, %f1049;
	// inline asm
	abs.f32 	%f257, %f258;
	// inline asm
	@%p1 bra 	BB13_100;

	ld.param.f32 	%f1045, [ResizeVerticalFilter_param_11];
	mul.f32 	%f19, %f257, %f1045;
	ld.param.u32 	%r1687, [ResizeVerticalFilter_param_9];
	setp.gt.s32 	%p17, %r1687, 2;
	@%p17 bra 	BB13_20;

	ld.param.u32 	%r1681, [ResizeVerticalFilter_param_9];
	setp.eq.s32 	%p23, %r1681, 0;
	@%p23 bra 	BB13_100;

	ld.param.u32 	%r1680, [ResizeVerticalFilter_param_9];
	setp.eq.s32 	%p24, %r1680, 1;
	@%p24 bra 	BB13_88;

	ld.param.u32 	%r1679, [ResizeVerticalFilter_param_9];
	setp.eq.s32 	%p25, %r1679, 2;
	@%p25 bra 	BB13_17;
	bra.uni 	BB13_99;

BB13_17:
	setp.lt.f32 	%p87, %f19, 0f3F800000;
	@%p87 bra 	BB13_89;

	setp.geu.f32 	%p88, %f19, 0f40000000;
	@%p88 bra 	BB13_99;

	ld.param.u32 	%r1696, [ResizeVerticalFilter_param_10];
	ld.global.f32 	%f365, [%r1696+24];
	ld.global.f32 	%f366, [%r1696+20];
	mad.f32 	%f367, %f19, %f365, %f366;
	ld.global.f32 	%f368, [%r1696+16];
	mad.f32 	%f369, %f19, %f367, %f368;
	ld.global.f32 	%f370, [%r1696+12];
	mad.f32 	%f1059, %f19, %f369, %f370;
	bra.uni 	BB13_101;

BB13_20:
	ld.param.u32 	%r1686, [ResizeVerticalFilter_param_9];
	setp.gt.s32 	%p18, %r1686, 4;
	@%p18 bra 	BB13_26;

	ld.param.u32 	%r1683, [ResizeVerticalFilter_param_9];
	setp.eq.s32 	%p21, %r1683, 3;
	@%p21 bra 	BB13_67;

	ld.param.u32 	%r1682, [ResizeVerticalFilter_param_9];
	setp.eq.s32 	%p22, %r1682, 4;
	@%p22 bra 	BB13_23;
	bra.uni 	BB13_99;

BB13_23:
	mul.f32 	%f31, %f19, 0f40490FDC;
	setp.eq.f32 	%p46, %f31, %f12;
	setp.eq.f32 	%p47, %f31, %f13;
	or.pred  	%p48, %p46, %p47;
	@%p48 bra 	BB13_65;

	// inline asm
	abs.f32 	%f297, %f31;
	// inline asm
	setp.gt.f32 	%p49, %f297, 0f473BA700;
	@%p49 bra 	BB13_49;

	mov.f32 	%f301, 0f3F22F983;
	mul.rn.f32 	%f300, %f31, %f301;
	// inline asm
	cvt.rni.f32.f32 	%f299, %f300;
	// inline asm
	cvt.rzi.s32.f32 	%r1732, %f299;
	cvt.rn.f32.s32 	%f302, %r1732;
	mov.f32 	%f303, 0f3FC90000;
	mul.rn.f32 	%f304, %f302, %f303;
	sub.f32 	%f305, %f31, %f304;
	mov.f32 	%f306, 0f39FD8000;
	mul.rn.f32 	%f307, %f302, %f306;
	sub.f32 	%f308, %f305, %f307;
	mov.f32 	%f309, 0f34A88000;
	mul.rn.f32 	%f310, %f302, %f309;
	sub.f32 	%f311, %f308, %f310;
	mov.f32 	%f312, 0f2E85A309;
	mul.rn.f32 	%f313, %f302, %f312;
	sub.f32 	%f1053, %f311, %f313;
	bra.uni 	BB13_61;

BB13_26:
	ld.param.u32 	%r1685, [ResizeVerticalFilter_param_9];
	add.s32 	%r580, %r1685, -9;
	setp.lt.u32 	%p19, %r580, 2;
	@%p19 bra 	BB13_90;

	ld.param.u32 	%r1684, [ResizeVerticalFilter_param_9];
	setp.ne.s32 	%p20, %r1684, 5;
	@%p20 bra 	BB13_99;

	mul.f32 	%f20, %f19, 0f40490FDC;
	setp.eq.f32 	%p26, %f20, %f12;
	setp.eq.f32 	%p27, %f20, %f13;
	or.pred  	%p28, %p26, %p27;
	@%p28 bra 	BB13_47;

	// inline asm
	abs.f32 	%f263, %f20;
	// inline asm
	setp.gt.f32 	%p29, %f263, 0f473BA700;
	@%p29 bra 	BB13_31;

	mov.f32 	%f267, 0f3F22F983;
	mul.rn.f32 	%f266, %f20, %f267;
	// inline asm
	cvt.rni.f32.f32 	%f265, %f266;
	// inline asm
	cvt.rzi.s32.f32 	%r1721, %f265;
	cvt.rn.f32.s32 	%f268, %r1721;
	mov.f32 	%f269, 0f3FC90000;
	mul.rn.f32 	%f270, %f268, %f269;
	sub.f32 	%f271, %f20, %f270;
	mov.f32 	%f272, 0f39FD8000;
	mul.rn.f32 	%f273, %f268, %f272;
	sub.f32 	%f274, %f271, %f273;
	mov.f32 	%f275, 0f34A88000;
	mul.rn.f32 	%f276, %f268, %f275;
	sub.f32 	%f277, %f274, %f276;
	mov.f32 	%f278, 0f2E85A309;
	mul.rn.f32 	%f279, %f268, %f278;
	sub.f32 	%f1051, %f277, %f279;
	bra.uni 	BB13_43;

BB13_31:
	mov.b32 	 %r42, %f20;
	and.b32  	%r1713, %r42, -2147483648;
	shr.u32 	%r44, %r42, 23;
	and.b32  	%r599, %r44, 255;
	add.s32 	%r600, %r599, -128;
	shl.b32 	%r601, %r42, 8;
	or.b32  	%r598, %r601, -2147483648;
	shr.u32 	%r602, %r600, 5;
	mov.u32 	%r603, 4;
	sub.s32 	%r604, %r603, %r602;
	ld.const.u32 	%r582, [__GPU_i2opi_f];
	mul.lo.s32 	%r605, %r582, %r598;
	// inline asm
	mul.hi.u32 	%r581, %r582, %r598;
	// inline asm
	st.local.u32 	[%r38], %r605;
	ld.const.u32 	%r585, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r606, %r585, %r598;
	// inline asm
	mul.hi.u32 	%r584, %r585, %r598;
	// inline asm
	mad.lo.s32 	%r607, %r585, %r598, %r581;
	setp.lt.u32 	%p30, %r607, %r606;
	selp.u32 	%r608, 1, 0, %p30;
	add.s32 	%r609, %r608, %r584;
	st.local.u32 	[%r38+4], %r607;
	ld.const.u32 	%r588, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r610, %r588, %r598;
	// inline asm
	mul.hi.u32 	%r587, %r588, %r598;
	// inline asm
	mad.lo.s32 	%r611, %r588, %r598, %r609;
	setp.lt.u32 	%p31, %r611, %r610;
	selp.u32 	%r612, 1, 0, %p31;
	add.s32 	%r613, %r612, %r587;
	st.local.u32 	[%r38+8], %r611;
	ld.const.u32 	%r591, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r614, %r591, %r598;
	// inline asm
	mul.hi.u32 	%r590, %r591, %r598;
	// inline asm
	mad.lo.s32 	%r615, %r591, %r598, %r613;
	setp.lt.u32 	%p32, %r615, %r614;
	selp.u32 	%r616, 1, 0, %p32;
	add.s32 	%r617, %r616, %r590;
	st.local.u32 	[%r38+12], %r615;
	ld.const.u32 	%r594, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r618, %r594, %r598;
	// inline asm
	mul.hi.u32 	%r593, %r594, %r598;
	// inline asm
	mad.lo.s32 	%r619, %r594, %r598, %r617;
	setp.lt.u32 	%p33, %r619, %r618;
	selp.u32 	%r620, 1, 0, %p33;
	add.s32 	%r621, %r620, %r593;
	st.local.u32 	[%r38+16], %r619;
	ld.const.u32 	%r597, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r622, %r597, %r598;
	// inline asm
	mul.hi.u32 	%r596, %r597, %r598;
	// inline asm
	mad.lo.s32 	%r623, %r597, %r598, %r621;
	setp.lt.u32 	%p34, %r623, %r622;
	selp.u32 	%r624, 1, 0, %p34;
	add.s32 	%r625, %r624, %r596;
	st.local.u32 	[%r38+20], %r623;
	st.local.u32 	[%r38+24], %r625;
	and.b32  	%r45, %r44, 31;
	shl.b32 	%r627, %r604, 2;
	add.s32 	%r628, %r627, %r38;
	add.s32 	%r46, %r628, -16;
	ld.local.u32 	%r1711, [%r628+8];
	ld.local.u32 	%r1712, [%r628+4];
	setp.eq.s32 	%p35, %r45, 0;
	@%p35 bra 	BB13_33;

	shl.b32 	%r629, %r1711, %r45;
	neg.s32 	%r630, %r44;
	and.b32  	%r631, %r630, 31;
	shr.u32 	%r632, %r1712, %r631;
	or.b32  	%r1711, %r632, %r629;
	ld.local.u32 	%r633, [%r46+16];
	shr.u32 	%r634, %r633, %r631;
	shl.b32 	%r635, %r1712, %r45;
	or.b32  	%r1712, %r634, %r635;

BB13_33:
	shr.u32 	%r636, %r1712, 30;
	shl.b32 	%r637, %r1711, 2;
	or.b32  	%r1717, %r636, %r637;
	shl.b32 	%r54, %r1712, 2;
	setp.ne.s32 	%p36, %r54, 0;
	selp.u32 	%r638, 1, 0, %p36;
	add.s32 	%r639, %r638, %r1717;
	setp.gt.u32 	%p37, %r639, -2147483648;
	selp.u32 	%r640, 1, 0, %p37;
	shr.u32 	%r641, %r1711, 30;
	add.s32 	%r642, %r640, %r641;
	neg.s32 	%r643, %r642;
	setp.lt.s32 	%p38, %r42, 0;
	selp.b32 	%r1721, %r643, %r642, %p38;
	@%p37 bra 	BB13_35;

	mov.u32 	%r1716, %r54;
	bra.uni 	BB13_36;

BB13_35:
	not.b32 	%r644, %r1717;
	neg.s32 	%r56, %r54;
	setp.eq.s32 	%p39, %r54, 0;
	selp.u32 	%r645, 1, 0, %p39;
	add.s32 	%r1717, %r645, %r644;
	xor.b32  	%r1713, %r1713, -2147483648;
	mov.u32 	%r1716, %r56;

BB13_36:
	mov.u32 	%r1715, %r1716;
	setp.gt.s32 	%p40, %r1717, 0;
	@%p40 bra 	BB13_38;

	mov.u32 	%r1720, 0;
	bra.uni 	BB13_40;

BB13_38:
	mov.u32 	%r1720, 0;

BB13_39:
	shr.u32 	%r648, %r1715, 31;
	shl.b32 	%r649, %r1717, 1;
	or.b32  	%r1717, %r648, %r649;
	shl.b32 	%r1715, %r1715, 1;
	add.s32 	%r1720, %r1720, -1;
	setp.gt.s32 	%p41, %r1717, 0;
	@%p41 bra 	BB13_39;

BB13_40:
	mul.lo.s32 	%r1719, %r1717, -921707870;
	mov.u32 	%r652, -921707870;
	// inline asm
	mul.hi.u32 	%r650, %r1717, %r652;
	// inline asm
	setp.gt.s32 	%p42, %r650, 0;
	mov.u32 	%r1718, %r650;
	@%p42 bra 	BB13_41;
	bra.uni 	BB13_42;

BB13_41:
	shl.b32 	%r653, %r650, 1;
	shr.u32 	%r654, %r1719, 31;
	or.b32  	%r1718, %r653, %r654;
	mul.lo.s32 	%r1719, %r1717, -1843415740;
	add.s32 	%r1720, %r1720, -1;

BB13_42:
	setp.ne.s32 	%p43, %r1719, 0;
	selp.u32 	%r655, 1, 0, %p43;
	add.s32 	%r656, %r655, %r1718;
	shr.u32 	%r657, %r656, 8;
	shr.u32 	%r658, %r656, 7;
	and.b32  	%r659, %r658, 1;
	shl.b32 	%r660, %r1720, 23;
	add.s32 	%r661, %r660, %r657;
	add.s32 	%r662, %r661, %r659;
	add.s32 	%r663, %r662, 1056964608;
	or.b32  	%r664, %r663, %r1713;
	mov.b32 	 %f1051, %r664;

BB13_43:
	add.s32 	%r79, %r1721, 1;
	and.b32  	%r665, %r79, 1;
	setp.eq.s32 	%p44, %r665, 0;
	mul.rn.f32 	%f24, %f1051, %f1051;
	@%p44 bra 	BB13_45;

	mov.f32 	%f280, 0f37CCF5CE;
	mul.rn.f32 	%f281, %f280, %f24;
	add.f32 	%f282, %f281, 0fBAB6061A;
	mul.rn.f32 	%f283, %f282, %f24;
	add.f32 	%f284, %f283, 0f3D2AAAA5;
	mul.rn.f32 	%f285, %f284, %f24;
	add.f32 	%f286, %f285, 0fBF000000;
	mul.rn.f32 	%f287, %f286, %f24;
	add.f32 	%f1052, %f287, 0f3F800000;
	bra.uni 	BB13_46;

BB13_45:
	mov.f32 	%f288, 0fB94CA1F9;
	mul.rn.f32 	%f289, %f288, %f24;
	add.f32 	%f290, %f289, 0f3C08839E;
	mul.rn.f32 	%f291, %f290, %f24;
	add.f32 	%f292, %f291, 0fBE2AAAA3;
	mul.rn.f32 	%f293, %f292, %f24;
	mul.rn.f32 	%f294, %f293, %f1051;
	add.f32 	%f1052, %f294, %f1051;

BB13_46:
	and.b32  	%r666, %r79, 2;
	setp.eq.s32 	%p45, %r666, 0;
	neg.f32 	%f295, %f1052;
	selp.f32 	%f1106, %f1052, %f295, %p45;
	bra.uni 	BB13_48;

BB13_47:
	mov.f32 	%f1106, %f14;

BB13_48:
	mad.f32 	%f296, %f1106, 0f3E23D70A, 0f3F000000;
	mad.f32 	%f1059, %f1106, %f296, 0f3EAE147B;
	bra.uni 	BB13_101;

BB13_49:
	mov.b32 	 %r81, %f31;
	and.b32  	%r1724, %r81, -2147483648;
	shr.u32 	%r83, %r81, 23;
	and.b32  	%r685, %r83, 255;
	add.s32 	%r686, %r685, -128;
	shl.b32 	%r687, %r81, 8;
	or.b32  	%r684, %r687, -2147483648;
	shr.u32 	%r688, %r686, 5;
	mov.u32 	%r689, 4;
	sub.s32 	%r690, %r689, %r688;
	ld.const.u32 	%r668, [__GPU_i2opi_f];
	mul.lo.s32 	%r691, %r668, %r684;
	// inline asm
	mul.hi.u32 	%r667, %r668, %r684;
	// inline asm
	st.local.u32 	[%r38], %r691;
	ld.const.u32 	%r671, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r692, %r671, %r684;
	// inline asm
	mul.hi.u32 	%r670, %r671, %r684;
	// inline asm
	mad.lo.s32 	%r693, %r671, %r684, %r667;
	setp.lt.u32 	%p50, %r693, %r692;
	selp.u32 	%r694, 1, 0, %p50;
	add.s32 	%r695, %r694, %r670;
	st.local.u32 	[%r38+4], %r693;
	ld.const.u32 	%r674, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r696, %r674, %r684;
	// inline asm
	mul.hi.u32 	%r673, %r674, %r684;
	// inline asm
	mad.lo.s32 	%r697, %r674, %r684, %r695;
	setp.lt.u32 	%p51, %r697, %r696;
	selp.u32 	%r698, 1, 0, %p51;
	add.s32 	%r699, %r698, %r673;
	st.local.u32 	[%r38+8], %r697;
	ld.const.u32 	%r677, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r700, %r677, %r684;
	// inline asm
	mul.hi.u32 	%r676, %r677, %r684;
	// inline asm
	mad.lo.s32 	%r701, %r677, %r684, %r699;
	setp.lt.u32 	%p52, %r701, %r700;
	selp.u32 	%r702, 1, 0, %p52;
	add.s32 	%r703, %r702, %r676;
	st.local.u32 	[%r38+12], %r701;
	ld.const.u32 	%r680, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r704, %r680, %r684;
	// inline asm
	mul.hi.u32 	%r679, %r680, %r684;
	// inline asm
	mad.lo.s32 	%r705, %r680, %r684, %r703;
	setp.lt.u32 	%p53, %r705, %r704;
	selp.u32 	%r706, 1, 0, %p53;
	add.s32 	%r707, %r706, %r679;
	st.local.u32 	[%r38+16], %r705;
	ld.const.u32 	%r683, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r708, %r683, %r684;
	// inline asm
	mul.hi.u32 	%r682, %r683, %r684;
	// inline asm
	mad.lo.s32 	%r709, %r683, %r684, %r707;
	setp.lt.u32 	%p54, %r709, %r708;
	selp.u32 	%r710, 1, 0, %p54;
	add.s32 	%r711, %r710, %r682;
	st.local.u32 	[%r38+20], %r709;
	st.local.u32 	[%r38+24], %r711;
	and.b32  	%r84, %r83, 31;
	shl.b32 	%r713, %r690, 2;
	add.s32 	%r714, %r713, %r38;
	add.s32 	%r85, %r714, -16;
	ld.local.u32 	%r1722, [%r714+8];
	ld.local.u32 	%r1723, [%r714+4];
	setp.eq.s32 	%p55, %r84, 0;
	@%p55 bra 	BB13_51;

	shl.b32 	%r715, %r1722, %r84;
	neg.s32 	%r716, %r83;
	and.b32  	%r717, %r716, 31;
	shr.u32 	%r718, %r1723, %r717;
	or.b32  	%r1722, %r718, %r715;
	ld.local.u32 	%r719, [%r85+16];
	shr.u32 	%r720, %r719, %r717;
	shl.b32 	%r721, %r1723, %r84;
	or.b32  	%r1723, %r720, %r721;

BB13_51:
	shr.u32 	%r722, %r1723, 30;
	shl.b32 	%r723, %r1722, 2;
	or.b32  	%r1728, %r722, %r723;
	shl.b32 	%r93, %r1723, 2;
	setp.ne.s32 	%p56, %r93, 0;
	selp.u32 	%r724, 1, 0, %p56;
	add.s32 	%r725, %r724, %r1728;
	setp.gt.u32 	%p57, %r725, -2147483648;
	selp.u32 	%r726, 1, 0, %p57;
	shr.u32 	%r727, %r1722, 30;
	add.s32 	%r728, %r726, %r727;
	neg.s32 	%r729, %r728;
	setp.lt.s32 	%p58, %r81, 0;
	selp.b32 	%r1732, %r729, %r728, %p58;
	@%p57 bra 	BB13_53;

	mov.u32 	%r1727, %r93;
	bra.uni 	BB13_54;

BB13_53:
	not.b32 	%r730, %r1728;
	neg.s32 	%r95, %r93;
	setp.eq.s32 	%p59, %r93, 0;
	selp.u32 	%r731, 1, 0, %p59;
	add.s32 	%r1728, %r731, %r730;
	xor.b32  	%r1724, %r1724, -2147483648;
	mov.u32 	%r1727, %r95;

BB13_54:
	mov.u32 	%r1726, %r1727;
	setp.gt.s32 	%p60, %r1728, 0;
	@%p60 bra 	BB13_56;

	mov.u32 	%r1731, 0;
	bra.uni 	BB13_58;

BB13_56:
	mov.u32 	%r1731, 0;

BB13_57:
	shr.u32 	%r734, %r1726, 31;
	shl.b32 	%r735, %r1728, 1;
	or.b32  	%r1728, %r734, %r735;
	shl.b32 	%r1726, %r1726, 1;
	add.s32 	%r1731, %r1731, -1;
	setp.gt.s32 	%p61, %r1728, 0;
	@%p61 bra 	BB13_57;

BB13_58:
	mul.lo.s32 	%r1730, %r1728, -921707870;
	mov.u32 	%r738, -921707870;
	// inline asm
	mul.hi.u32 	%r736, %r1728, %r738;
	// inline asm
	setp.gt.s32 	%p62, %r736, 0;
	mov.u32 	%r1729, %r736;
	@%p62 bra 	BB13_59;
	bra.uni 	BB13_60;

BB13_59:
	shl.b32 	%r739, %r736, 1;
	shr.u32 	%r740, %r1730, 31;
	or.b32  	%r1729, %r739, %r740;
	mul.lo.s32 	%r1730, %r1728, -1843415740;
	add.s32 	%r1731, %r1731, -1;

BB13_60:
	setp.ne.s32 	%p63, %r1730, 0;
	selp.u32 	%r741, 1, 0, %p63;
	add.s32 	%r742, %r741, %r1729;
	shr.u32 	%r743, %r742, 8;
	shr.u32 	%r744, %r742, 7;
	and.b32  	%r745, %r744, 1;
	shl.b32 	%r746, %r1731, 23;
	add.s32 	%r747, %r746, %r743;
	add.s32 	%r748, %r747, %r745;
	add.s32 	%r749, %r748, 1056964608;
	or.b32  	%r750, %r749, %r1724;
	mov.b32 	 %f1053, %r750;

BB13_61:
	add.s32 	%r118, %r1732, 1;
	and.b32  	%r751, %r118, 1;
	setp.eq.s32 	%p64, %r751, 0;
	mul.rn.f32 	%f35, %f1053, %f1053;
	@%p64 bra 	BB13_63;

	mov.f32 	%f314, 0f37CCF5CE;
	mul.rn.f32 	%f315, %f314, %f35;
	add.f32 	%f316, %f315, 0fBAB6061A;
	mul.rn.f32 	%f317, %f316, %f35;
	add.f32 	%f318, %f317, 0f3D2AAAA5;
	mul.rn.f32 	%f319, %f318, %f35;
	add.f32 	%f320, %f319, 0fBF000000;
	mul.rn.f32 	%f321, %f320, %f35;
	add.f32 	%f1054, %f321, 0f3F800000;
	bra.uni 	BB13_64;

BB13_63:
	mov.f32 	%f322, 0fB94CA1F9;
	mul.rn.f32 	%f323, %f322, %f35;
	add.f32 	%f324, %f323, 0f3C08839E;
	mul.rn.f32 	%f325, %f324, %f35;
	add.f32 	%f326, %f325, 0fBE2AAAA3;
	mul.rn.f32 	%f327, %f326, %f35;
	mul.rn.f32 	%f328, %f327, %f1053;
	add.f32 	%f1054, %f328, %f1053;

BB13_64:
	and.b32  	%r752, %r118, 2;
	setp.eq.s32 	%p65, %r752, 0;
	neg.f32 	%f329, %f1054;
	selp.f32 	%f1105, %f1054, %f329, %p65;
	bra.uni 	BB13_66;

BB13_65:
	mov.f32 	%f1105, %f14;

BB13_66:
	mad.f32 	%f1059, %f1105, 0f3EEB851F, 0f3F0A3D71;
	bra.uni 	BB13_101;

BB13_67:
	mul.f32 	%f42, %f19, 0f40490FDC;
	setp.eq.f32 	%p66, %f42, %f12;
	setp.eq.f32 	%p67, %f42, %f13;
	or.pred  	%p68, %p66, %p67;
	@%p68 bra 	BB13_86;

	// inline asm
	abs.f32 	%f330, %f42;
	// inline asm
	setp.gt.f32 	%p69, %f330, 0f473BA700;
	@%p69 bra 	BB13_70;

	mov.f32 	%f334, 0f3F22F983;
	mul.rn.f32 	%f333, %f42, %f334;
	// inline asm
	cvt.rni.f32.f32 	%f332, %f333;
	// inline asm
	cvt.rzi.s32.f32 	%r1743, %f332;
	cvt.rn.f32.s32 	%f335, %r1743;
	mov.f32 	%f336, 0f3FC90000;
	mul.rn.f32 	%f337, %f335, %f336;
	sub.f32 	%f338, %f42, %f337;
	mov.f32 	%f339, 0f39FD8000;
	mul.rn.f32 	%f340, %f335, %f339;
	sub.f32 	%f341, %f338, %f340;
	mov.f32 	%f342, 0f34A88000;
	mul.rn.f32 	%f343, %f335, %f342;
	sub.f32 	%f344, %f341, %f343;
	mov.f32 	%f345, 0f2E85A309;
	mul.rn.f32 	%f346, %f335, %f345;
	sub.f32 	%f1055, %f344, %f346;
	bra.uni 	BB13_82;

BB13_70:
	mov.b32 	 %r120, %f42;
	and.b32  	%r1735, %r120, -2147483648;
	shr.u32 	%r122, %r120, 23;
	and.b32  	%r771, %r122, 255;
	add.s32 	%r772, %r771, -128;
	shl.b32 	%r773, %r120, 8;
	or.b32  	%r770, %r773, -2147483648;
	shr.u32 	%r774, %r772, 5;
	mov.u32 	%r775, 4;
	sub.s32 	%r776, %r775, %r774;
	ld.const.u32 	%r754, [__GPU_i2opi_f];
	mul.lo.s32 	%r777, %r754, %r770;
	// inline asm
	mul.hi.u32 	%r753, %r754, %r770;
	// inline asm
	st.local.u32 	[%r38], %r777;
	ld.const.u32 	%r757, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r778, %r757, %r770;
	// inline asm
	mul.hi.u32 	%r756, %r757, %r770;
	// inline asm
	mad.lo.s32 	%r779, %r757, %r770, %r753;
	setp.lt.u32 	%p70, %r779, %r778;
	selp.u32 	%r780, 1, 0, %p70;
	add.s32 	%r781, %r780, %r756;
	st.local.u32 	[%r38+4], %r779;
	ld.const.u32 	%r760, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r782, %r760, %r770;
	// inline asm
	mul.hi.u32 	%r759, %r760, %r770;
	// inline asm
	mad.lo.s32 	%r783, %r760, %r770, %r781;
	setp.lt.u32 	%p71, %r783, %r782;
	selp.u32 	%r784, 1, 0, %p71;
	add.s32 	%r785, %r784, %r759;
	st.local.u32 	[%r38+8], %r783;
	ld.const.u32 	%r763, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r786, %r763, %r770;
	// inline asm
	mul.hi.u32 	%r762, %r763, %r770;
	// inline asm
	mad.lo.s32 	%r787, %r763, %r770, %r785;
	setp.lt.u32 	%p72, %r787, %r786;
	selp.u32 	%r788, 1, 0, %p72;
	add.s32 	%r789, %r788, %r762;
	st.local.u32 	[%r38+12], %r787;
	ld.const.u32 	%r766, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r790, %r766, %r770;
	// inline asm
	mul.hi.u32 	%r765, %r766, %r770;
	// inline asm
	mad.lo.s32 	%r791, %r766, %r770, %r789;
	setp.lt.u32 	%p73, %r791, %r790;
	selp.u32 	%r792, 1, 0, %p73;
	add.s32 	%r793, %r792, %r765;
	st.local.u32 	[%r38+16], %r791;
	ld.const.u32 	%r769, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r794, %r769, %r770;
	// inline asm
	mul.hi.u32 	%r768, %r769, %r770;
	// inline asm
	mad.lo.s32 	%r795, %r769, %r770, %r793;
	setp.lt.u32 	%p74, %r795, %r794;
	selp.u32 	%r796, 1, 0, %p74;
	add.s32 	%r797, %r796, %r768;
	st.local.u32 	[%r38+20], %r795;
	st.local.u32 	[%r38+24], %r797;
	and.b32  	%r123, %r122, 31;
	shl.b32 	%r799, %r776, 2;
	add.s32 	%r800, %r799, %r38;
	add.s32 	%r124, %r800, -16;
	ld.local.u32 	%r1733, [%r800+8];
	ld.local.u32 	%r1734, [%r800+4];
	setp.eq.s32 	%p75, %r123, 0;
	@%p75 bra 	BB13_72;

	shl.b32 	%r801, %r1733, %r123;
	neg.s32 	%r802, %r122;
	and.b32  	%r803, %r802, 31;
	shr.u32 	%r804, %r1734, %r803;
	or.b32  	%r1733, %r804, %r801;
	ld.local.u32 	%r805, [%r124+16];
	shr.u32 	%r806, %r805, %r803;
	shl.b32 	%r807, %r1734, %r123;
	or.b32  	%r1734, %r806, %r807;

BB13_72:
	shr.u32 	%r808, %r1734, 30;
	shl.b32 	%r809, %r1733, 2;
	or.b32  	%r1739, %r808, %r809;
	shl.b32 	%r132, %r1734, 2;
	setp.ne.s32 	%p76, %r132, 0;
	selp.u32 	%r810, 1, 0, %p76;
	add.s32 	%r811, %r810, %r1739;
	setp.gt.u32 	%p77, %r811, -2147483648;
	selp.u32 	%r812, 1, 0, %p77;
	shr.u32 	%r813, %r1733, 30;
	add.s32 	%r814, %r812, %r813;
	neg.s32 	%r815, %r814;
	setp.lt.s32 	%p78, %r120, 0;
	selp.b32 	%r1743, %r815, %r814, %p78;
	@%p77 bra 	BB13_74;

	mov.u32 	%r1738, %r132;
	bra.uni 	BB13_75;

BB13_74:
	not.b32 	%r816, %r1739;
	neg.s32 	%r134, %r132;
	setp.eq.s32 	%p79, %r132, 0;
	selp.u32 	%r817, 1, 0, %p79;
	add.s32 	%r1739, %r817, %r816;
	xor.b32  	%r1735, %r1735, -2147483648;
	mov.u32 	%r1738, %r134;

BB13_75:
	mov.u32 	%r1737, %r1738;
	setp.gt.s32 	%p80, %r1739, 0;
	@%p80 bra 	BB13_77;

	mov.u32 	%r1742, 0;
	bra.uni 	BB13_79;

BB13_77:
	mov.u32 	%r1742, 0;

BB13_78:
	shr.u32 	%r820, %r1737, 31;
	shl.b32 	%r821, %r1739, 1;
	or.b32  	%r1739, %r820, %r821;
	shl.b32 	%r1737, %r1737, 1;
	add.s32 	%r1742, %r1742, -1;
	setp.gt.s32 	%p81, %r1739, 0;
	@%p81 bra 	BB13_78;

BB13_79:
	mul.lo.s32 	%r1741, %r1739, -921707870;
	mov.u32 	%r824, -921707870;
	// inline asm
	mul.hi.u32 	%r822, %r1739, %r824;
	// inline asm
	setp.gt.s32 	%p82, %r822, 0;
	mov.u32 	%r1740, %r822;
	@%p82 bra 	BB13_80;
	bra.uni 	BB13_81;

BB13_80:
	shl.b32 	%r825, %r822, 1;
	shr.u32 	%r826, %r1741, 31;
	or.b32  	%r1740, %r825, %r826;
	mul.lo.s32 	%r1741, %r1739, -1843415740;
	add.s32 	%r1742, %r1742, -1;

BB13_81:
	setp.ne.s32 	%p83, %r1741, 0;
	selp.u32 	%r827, 1, 0, %p83;
	add.s32 	%r828, %r827, %r1740;
	shr.u32 	%r829, %r828, 8;
	shr.u32 	%r830, %r828, 7;
	and.b32  	%r831, %r830, 1;
	shl.b32 	%r832, %r1742, 23;
	add.s32 	%r833, %r832, %r829;
	add.s32 	%r834, %r833, %r831;
	add.s32 	%r835, %r834, 1056964608;
	or.b32  	%r836, %r835, %r1735;
	mov.b32 	 %f1055, %r836;

BB13_82:
	add.s32 	%r157, %r1743, 1;
	and.b32  	%r837, %r157, 1;
	setp.eq.s32 	%p84, %r837, 0;
	mul.rn.f32 	%f46, %f1055, %f1055;
	@%p84 bra 	BB13_84;

	mov.f32 	%f347, 0f37CCF5CE;
	mul.rn.f32 	%f348, %f347, %f46;
	add.f32 	%f349, %f348, 0fBAB6061A;
	mul.rn.f32 	%f350, %f349, %f46;
	add.f32 	%f351, %f350, 0f3D2AAAA5;
	mul.rn.f32 	%f352, %f351, %f46;
	add.f32 	%f353, %f352, 0fBF000000;
	mul.rn.f32 	%f354, %f353, %f46;
	add.f32 	%f1056, %f354, 0f3F800000;
	bra.uni 	BB13_85;

BB13_84:
	mov.f32 	%f355, 0fB94CA1F9;
	mul.rn.f32 	%f356, %f355, %f46;
	add.f32 	%f357, %f356, 0f3C08839E;
	mul.rn.f32 	%f358, %f357, %f46;
	add.f32 	%f359, %f358, 0fBE2AAAA3;
	mul.rn.f32 	%f360, %f359, %f46;
	mul.rn.f32 	%f361, %f360, %f1055;
	add.f32 	%f1056, %f361, %f1055;

BB13_85:
	and.b32  	%r838, %r157, 2;
	setp.eq.s32 	%p85, %r838, 0;
	neg.f32 	%f362, %f1056;
	selp.f32 	%f1104, %f1056, %f362, %p85;
	bra.uni 	BB13_87;

BB13_86:
	mov.f32 	%f1104, %f14;

BB13_87:
	mad.f32 	%f1059, %f1104, 0f3F000000, 0f3F000000;
	bra.uni 	BB13_101;

BB13_88:
	setp.lt.f32 	%p86, %f19, 0f3F800000;
	sub.f32 	%f364, %f234, %f19;
	selp.f32 	%f1059, %f364, 0f00000000, %p86;
	bra.uni 	BB13_101;

BB13_89:
	ld.param.u32 	%r1695, [ResizeVerticalFilter_param_10];
	ld.global.f32 	%f371, [%r1695];
	ld.global.f32 	%f372, [%r1695+8];
	ld.global.f32 	%f373, [%r1695+4];
	mad.f32 	%f374, %f19, %f372, %f373;
	mul.f32 	%f375, %f19, %f374;
	mad.f32 	%f1059, %f19, %f375, %f371;
	bra.uni 	BB13_101;

BB13_90:
	setp.eq.f32 	%p89, %f19, 0f00000000;
	@%p89 bra 	BB13_100;

	mul.f32 	%f56, %f19, 0f40490FDC;
	setp.eq.f32 	%p90, %f19, %f12;
	@%p90 bra 	BB13_97;

	setp.eq.f32 	%p91, %f19, %f13;
	or.pred  	%p93, %p91, %p89;
	@%p93 bra 	BB13_97;

	mov.f32 	%f380, 0f40000000;
	mul.rn.f32 	%f377, %f380, %f19;
	// inline asm
	cvt.rni.f32.f32 	%f376, %f377;
	// inline asm
	cvt.rzi.s32.f32 	%r839, %f376;
	neg.f32 	%f381, %f376;
	mul.rn.f32 	%f383, %f381, %f237;
	add.f32 	%f384, %f383, %f19;
	mov.f32 	%f385, 0f40490FDB;
	mul.rn.f32 	%f386, %f384, %f385;
	// inline asm
	abs.f32 	%f378, %f19;
	// inline asm
	setp.gt.f32 	%p94, %f378, 0f4B800000;
	selp.f32 	%f57, 0f00000000, %f386, %p94;
	selp.b32 	%r158, 0, %r839, %p94;
	and.b32  	%r840, %r158, 1;
	setp.eq.s32 	%p95, %r840, 0;
	mul.rn.f32 	%f58, %f57, %f57;
	@%p95 bra 	BB13_95;

	mov.f32 	%f387, 0f37CCF5CE;
	mul.rn.f32 	%f388, %f387, %f58;
	add.f32 	%f389, %f388, 0fBAB6061A;
	mul.rn.f32 	%f390, %f389, %f58;
	add.f32 	%f391, %f390, 0f3D2AAAA5;
	mul.rn.f32 	%f392, %f391, %f58;
	add.f32 	%f393, %f392, 0fBF000000;
	mul.rn.f32 	%f394, %f393, %f58;
	add.f32 	%f1057, %f394, 0f3F800000;
	bra.uni 	BB13_96;

BB13_95:
	mov.f32 	%f395, 0fB94CA1F9;
	mul.rn.f32 	%f396, %f395, %f58;
	add.f32 	%f397, %f396, 0f3C08839E;
	mul.rn.f32 	%f398, %f397, %f58;
	add.f32 	%f399, %f398, 0fBE2AAAA3;
	mul.rn.f32 	%f400, %f399, %f58;
	mul.rn.f32 	%f401, %f400, %f57;
	add.f32 	%f1057, %f401, %f57;

BB13_96:
	and.b32  	%r841, %r158, 2;
	setp.eq.s32 	%p96, %r841, 0;
	neg.f32 	%f402, %f1057;
	selp.f32 	%f1058, %f1057, %f402, %p96;
	bra.uni 	BB13_98;

BB13_97:
	mov.f32 	%f403, 0f00000000;
	mul.rn.f32 	%f1058, %f19, %f403;

BB13_98:
	div.full.f32 	%f1059, %f1058, %f56;
	bra.uni 	BB13_101;

BB13_99:
	mov.f32 	%f1059, 0f00000000;
	bra.uni 	BB13_101;

BB13_100:
	mov.f32 	%f1059, 0f3F800000;

BB13_101:
	ld.param.u32 	%r1669, [ResizeVerticalFilter_param_8];
	setp.gt.s32 	%p97, %r1669, 2;
	@%p97 bra 	BB13_108;

	ld.param.u32 	%r1663, [ResizeVerticalFilter_param_8];
	setp.eq.s32 	%p103, %r1663, 0;
	@%p103 bra 	BB13_179;

	ld.param.u32 	%r1662, [ResizeVerticalFilter_param_8];
	setp.eq.s32 	%p104, %r1662, 1;
	@%p104 bra 	BB13_176;

	ld.param.u32 	%r1661, [ResizeVerticalFilter_param_8];
	setp.eq.s32 	%p105, %r1661, 2;
	@%p105 bra 	BB13_105;
	bra.uni 	BB13_188;

BB13_105:
	setp.lt.f32 	%p167, %f257, 0f3F800000;
	@%p167 bra 	BB13_177;

	setp.geu.f32 	%p168, %f257, 0f40000000;
	@%p168 bra 	BB13_188;

	ld.param.u32 	%r1694, [ResizeVerticalFilter_param_10];
	ld.global.f32 	%f508, [%r1694+24];
	ld.global.f32 	%f509, [%r1694+20];
	mad.f32 	%f510, %f257, %f508, %f509;
	ld.global.f32 	%f511, [%r1694+16];
	mad.f32 	%f512, %f257, %f510, %f511;
	ld.global.f32 	%f513, [%r1694+12];
	mad.f32 	%f101, %f257, %f512, %f513;
	mov.f32 	%f1068, %f101;
	bra.uni 	BB13_189;

BB13_108:
	ld.param.u32 	%r1668, [ResizeVerticalFilter_param_8];
	setp.gt.s32 	%p98, %r1668, 4;
	@%p98 bra 	BB13_114;

	ld.param.u32 	%r1665, [ResizeVerticalFilter_param_8];
	setp.eq.s32 	%p101, %r1665, 3;
	@%p101 bra 	BB13_155;

	ld.param.u32 	%r1664, [ResizeVerticalFilter_param_8];
	setp.eq.s32 	%p102, %r1664, 4;
	@%p102 bra 	BB13_111;
	bra.uni 	BB13_188;

BB13_111:
	mul.f32 	%f78, %f257, 0f40490FDC;
	setp.eq.f32 	%p126, %f78, %f12;
	setp.eq.f32 	%p127, %f78, %f13;
	or.pred  	%p128, %p126, %p127;
	@%p128 bra 	BB13_153;

	// inline asm
	abs.f32 	%f440, %f78;
	// inline asm
	setp.gt.f32 	%p129, %f440, 0f473BA700;
	@%p129 bra 	BB13_137;

	mov.f32 	%f444, 0f3F22F983;
	mul.rn.f32 	%f443, %f78, %f444;
	// inline asm
	cvt.rni.f32.f32 	%f442, %f443;
	// inline asm
	cvt.rzi.s32.f32 	%r1765, %f442;
	cvt.rn.f32.s32 	%f445, %r1765;
	mov.f32 	%f446, 0f3FC90000;
	mul.rn.f32 	%f447, %f445, %f446;
	sub.f32 	%f448, %f78, %f447;
	mov.f32 	%f449, 0f39FD8000;
	mul.rn.f32 	%f450, %f445, %f449;
	sub.f32 	%f451, %f448, %f450;
	mov.f32 	%f452, 0f34A88000;
	mul.rn.f32 	%f453, %f445, %f452;
	sub.f32 	%f454, %f451, %f453;
	mov.f32 	%f455, 0f2E85A309;
	mul.rn.f32 	%f456, %f445, %f455;
	sub.f32 	%f1062, %f454, %f456;
	bra.uni 	BB13_149;

BB13_114:
	ld.param.u32 	%r1667, [ResizeVerticalFilter_param_8];
	add.s32 	%r842, %r1667, -9;
	setp.lt.u32 	%p99, %r842, 2;
	@%p99 bra 	BB13_178;

	ld.param.u32 	%r1666, [ResizeVerticalFilter_param_8];
	setp.ne.s32 	%p100, %r1666, 5;
	@%p100 bra 	BB13_188;

	mul.f32 	%f67, %f257, 0f40490FDC;
	setp.eq.f32 	%p106, %f67, %f12;
	setp.eq.f32 	%p107, %f67, %f13;
	or.pred  	%p108, %p106, %p107;
	@%p108 bra 	BB13_135;

	// inline asm
	abs.f32 	%f406, %f67;
	// inline asm
	setp.gt.f32 	%p109, %f406, 0f473BA700;
	@%p109 bra 	BB13_119;

	mov.f32 	%f410, 0f3F22F983;
	mul.rn.f32 	%f409, %f67, %f410;
	// inline asm
	cvt.rni.f32.f32 	%f408, %f409;
	// inline asm
	cvt.rzi.s32.f32 	%r1754, %f408;
	cvt.rn.f32.s32 	%f411, %r1754;
	mov.f32 	%f412, 0f3FC90000;
	mul.rn.f32 	%f413, %f411, %f412;
	sub.f32 	%f414, %f67, %f413;
	mov.f32 	%f415, 0f39FD8000;
	mul.rn.f32 	%f416, %f411, %f415;
	sub.f32 	%f417, %f414, %f416;
	mov.f32 	%f418, 0f34A88000;
	mul.rn.f32 	%f419, %f411, %f418;
	sub.f32 	%f420, %f417, %f419;
	mov.f32 	%f421, 0f2E85A309;
	mul.rn.f32 	%f422, %f411, %f421;
	sub.f32 	%f1060, %f420, %f422;
	bra.uni 	BB13_131;

BB13_119:
	mov.b32 	 %r160, %f67;
	and.b32  	%r1746, %r160, -2147483648;
	shr.u32 	%r162, %r160, 23;
	and.b32  	%r861, %r162, 255;
	add.s32 	%r862, %r861, -128;
	shl.b32 	%r863, %r160, 8;
	or.b32  	%r860, %r863, -2147483648;
	shr.u32 	%r864, %r862, 5;
	mov.u32 	%r865, 4;
	sub.s32 	%r866, %r865, %r864;
	ld.const.u32 	%r844, [__GPU_i2opi_f];
	mul.lo.s32 	%r867, %r844, %r860;
	// inline asm
	mul.hi.u32 	%r843, %r844, %r860;
	// inline asm
	st.local.u32 	[%r38], %r867;
	ld.const.u32 	%r847, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r868, %r847, %r860;
	// inline asm
	mul.hi.u32 	%r846, %r847, %r860;
	// inline asm
	mad.lo.s32 	%r869, %r847, %r860, %r843;
	setp.lt.u32 	%p110, %r869, %r868;
	selp.u32 	%r870, 1, 0, %p110;
	add.s32 	%r871, %r870, %r846;
	st.local.u32 	[%r38+4], %r869;
	ld.const.u32 	%r850, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r872, %r850, %r860;
	// inline asm
	mul.hi.u32 	%r849, %r850, %r860;
	// inline asm
	mad.lo.s32 	%r873, %r850, %r860, %r871;
	setp.lt.u32 	%p111, %r873, %r872;
	selp.u32 	%r874, 1, 0, %p111;
	add.s32 	%r875, %r874, %r849;
	st.local.u32 	[%r38+8], %r873;
	ld.const.u32 	%r853, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r876, %r853, %r860;
	// inline asm
	mul.hi.u32 	%r852, %r853, %r860;
	// inline asm
	mad.lo.s32 	%r877, %r853, %r860, %r875;
	setp.lt.u32 	%p112, %r877, %r876;
	selp.u32 	%r878, 1, 0, %p112;
	add.s32 	%r879, %r878, %r852;
	st.local.u32 	[%r38+12], %r877;
	ld.const.u32 	%r856, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r880, %r856, %r860;
	// inline asm
	mul.hi.u32 	%r855, %r856, %r860;
	// inline asm
	mad.lo.s32 	%r881, %r856, %r860, %r879;
	setp.lt.u32 	%p113, %r881, %r880;
	selp.u32 	%r882, 1, 0, %p113;
	add.s32 	%r883, %r882, %r855;
	st.local.u32 	[%r38+16], %r881;
	ld.const.u32 	%r859, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r884, %r859, %r860;
	// inline asm
	mul.hi.u32 	%r858, %r859, %r860;
	// inline asm
	mad.lo.s32 	%r885, %r859, %r860, %r883;
	setp.lt.u32 	%p114, %r885, %r884;
	selp.u32 	%r886, 1, 0, %p114;
	add.s32 	%r887, %r886, %r858;
	st.local.u32 	[%r38+20], %r885;
	st.local.u32 	[%r38+24], %r887;
	and.b32  	%r163, %r162, 31;
	shl.b32 	%r889, %r866, 2;
	add.s32 	%r890, %r889, %r38;
	add.s32 	%r164, %r890, -16;
	ld.local.u32 	%r1744, [%r890+8];
	ld.local.u32 	%r1745, [%r890+4];
	setp.eq.s32 	%p115, %r163, 0;
	@%p115 bra 	BB13_121;

	shl.b32 	%r891, %r1744, %r163;
	neg.s32 	%r892, %r162;
	and.b32  	%r893, %r892, 31;
	shr.u32 	%r894, %r1745, %r893;
	or.b32  	%r1744, %r894, %r891;
	ld.local.u32 	%r895, [%r164+16];
	shr.u32 	%r896, %r895, %r893;
	shl.b32 	%r897, %r1745, %r163;
	or.b32  	%r1745, %r896, %r897;

BB13_121:
	shr.u32 	%r898, %r1745, 30;
	shl.b32 	%r899, %r1744, 2;
	or.b32  	%r1750, %r898, %r899;
	shl.b32 	%r172, %r1745, 2;
	setp.ne.s32 	%p116, %r172, 0;
	selp.u32 	%r900, 1, 0, %p116;
	add.s32 	%r901, %r900, %r1750;
	setp.gt.u32 	%p117, %r901, -2147483648;
	selp.u32 	%r902, 1, 0, %p117;
	shr.u32 	%r903, %r1744, 30;
	add.s32 	%r904, %r902, %r903;
	neg.s32 	%r905, %r904;
	setp.lt.s32 	%p118, %r160, 0;
	selp.b32 	%r1754, %r905, %r904, %p118;
	@%p117 bra 	BB13_123;

	mov.u32 	%r1749, %r172;
	bra.uni 	BB13_124;

BB13_123:
	not.b32 	%r906, %r1750;
	neg.s32 	%r174, %r172;
	setp.eq.s32 	%p119, %r172, 0;
	selp.u32 	%r907, 1, 0, %p119;
	add.s32 	%r1750, %r907, %r906;
	xor.b32  	%r1746, %r1746, -2147483648;
	mov.u32 	%r1749, %r174;

BB13_124:
	mov.u32 	%r1748, %r1749;
	setp.gt.s32 	%p120, %r1750, 0;
	@%p120 bra 	BB13_126;

	mov.u32 	%r1753, 0;
	bra.uni 	BB13_128;

BB13_126:
	mov.u32 	%r1753, 0;

BB13_127:
	shr.u32 	%r910, %r1748, 31;
	shl.b32 	%r911, %r1750, 1;
	or.b32  	%r1750, %r910, %r911;
	shl.b32 	%r1748, %r1748, 1;
	add.s32 	%r1753, %r1753, -1;
	setp.gt.s32 	%p121, %r1750, 0;
	@%p121 bra 	BB13_127;

BB13_128:
	mul.lo.s32 	%r1752, %r1750, -921707870;
	mov.u32 	%r914, -921707870;
	// inline asm
	mul.hi.u32 	%r912, %r1750, %r914;
	// inline asm
	setp.gt.s32 	%p122, %r912, 0;
	mov.u32 	%r1751, %r912;
	@%p122 bra 	BB13_129;
	bra.uni 	BB13_130;

BB13_129:
	shl.b32 	%r915, %r912, 1;
	shr.u32 	%r916, %r1752, 31;
	or.b32  	%r1751, %r915, %r916;
	mul.lo.s32 	%r1752, %r1750, -1843415740;
	add.s32 	%r1753, %r1753, -1;

BB13_130:
	setp.ne.s32 	%p123, %r1752, 0;
	selp.u32 	%r917, 1, 0, %p123;
	add.s32 	%r918, %r917, %r1751;
	shr.u32 	%r919, %r918, 8;
	shr.u32 	%r920, %r918, 7;
	and.b32  	%r921, %r920, 1;
	shl.b32 	%r922, %r1753, 23;
	add.s32 	%r923, %r922, %r919;
	add.s32 	%r924, %r923, %r921;
	add.s32 	%r925, %r924, 1056964608;
	or.b32  	%r926, %r925, %r1746;
	mov.b32 	 %f1060, %r926;

BB13_131:
	add.s32 	%r197, %r1754, 1;
	and.b32  	%r927, %r197, 1;
	setp.eq.s32 	%p124, %r927, 0;
	mul.rn.f32 	%f71, %f1060, %f1060;
	@%p124 bra 	BB13_133;

	mov.f32 	%f423, 0f37CCF5CE;
	mul.rn.f32 	%f424, %f423, %f71;
	add.f32 	%f425, %f424, 0fBAB6061A;
	mul.rn.f32 	%f426, %f425, %f71;
	add.f32 	%f427, %f426, 0f3D2AAAA5;
	mul.rn.f32 	%f428, %f427, %f71;
	add.f32 	%f429, %f428, 0fBF000000;
	mul.rn.f32 	%f430, %f429, %f71;
	add.f32 	%f1061, %f430, 0f3F800000;
	bra.uni 	BB13_134;

BB13_133:
	mov.f32 	%f431, 0fB94CA1F9;
	mul.rn.f32 	%f432, %f431, %f71;
	add.f32 	%f433, %f432, 0f3C08839E;
	mul.rn.f32 	%f434, %f433, %f71;
	add.f32 	%f435, %f434, 0fBE2AAAA3;
	mul.rn.f32 	%f436, %f435, %f71;
	mul.rn.f32 	%f437, %f436, %f1060;
	add.f32 	%f1061, %f437, %f1060;

BB13_134:
	and.b32  	%r928, %r197, 2;
	setp.eq.s32 	%p125, %r928, 0;
	neg.f32 	%f438, %f1061;
	selp.f32 	%f1103, %f1061, %f438, %p125;
	bra.uni 	BB13_136;

BB13_135:
	mov.f32 	%f1103, %f14;

BB13_136:
	mad.f32 	%f439, %f1103, 0f3E23D70A, 0f3F000000;
	mad.f32 	%f77, %f1103, %f439, 0f3EAE147B;
	mov.f32 	%f1068, %f77;
	bra.uni 	BB13_189;

BB13_137:
	mov.b32 	 %r199, %f78;
	and.b32  	%r1757, %r199, -2147483648;
	shr.u32 	%r201, %r199, 23;
	and.b32  	%r947, %r201, 255;
	add.s32 	%r948, %r947, -128;
	shl.b32 	%r949, %r199, 8;
	or.b32  	%r946, %r949, -2147483648;
	shr.u32 	%r950, %r948, 5;
	mov.u32 	%r951, 4;
	sub.s32 	%r952, %r951, %r950;
	ld.const.u32 	%r930, [__GPU_i2opi_f];
	mul.lo.s32 	%r953, %r930, %r946;
	// inline asm
	mul.hi.u32 	%r929, %r930, %r946;
	// inline asm
	st.local.u32 	[%r38], %r953;
	ld.const.u32 	%r933, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r954, %r933, %r946;
	// inline asm
	mul.hi.u32 	%r932, %r933, %r946;
	// inline asm
	mad.lo.s32 	%r955, %r933, %r946, %r929;
	setp.lt.u32 	%p130, %r955, %r954;
	selp.u32 	%r956, 1, 0, %p130;
	add.s32 	%r957, %r956, %r932;
	st.local.u32 	[%r38+4], %r955;
	ld.const.u32 	%r936, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r958, %r936, %r946;
	// inline asm
	mul.hi.u32 	%r935, %r936, %r946;
	// inline asm
	mad.lo.s32 	%r959, %r936, %r946, %r957;
	setp.lt.u32 	%p131, %r959, %r958;
	selp.u32 	%r960, 1, 0, %p131;
	add.s32 	%r961, %r960, %r935;
	st.local.u32 	[%r38+8], %r959;
	ld.const.u32 	%r939, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r962, %r939, %r946;
	// inline asm
	mul.hi.u32 	%r938, %r939, %r946;
	// inline asm
	mad.lo.s32 	%r963, %r939, %r946, %r961;
	setp.lt.u32 	%p132, %r963, %r962;
	selp.u32 	%r964, 1, 0, %p132;
	add.s32 	%r965, %r964, %r938;
	st.local.u32 	[%r38+12], %r963;
	ld.const.u32 	%r942, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r966, %r942, %r946;
	// inline asm
	mul.hi.u32 	%r941, %r942, %r946;
	// inline asm
	mad.lo.s32 	%r967, %r942, %r946, %r965;
	setp.lt.u32 	%p133, %r967, %r966;
	selp.u32 	%r968, 1, 0, %p133;
	add.s32 	%r969, %r968, %r941;
	st.local.u32 	[%r38+16], %r967;
	ld.const.u32 	%r945, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r970, %r945, %r946;
	// inline asm
	mul.hi.u32 	%r944, %r945, %r946;
	// inline asm
	mad.lo.s32 	%r971, %r945, %r946, %r969;
	setp.lt.u32 	%p134, %r971, %r970;
	selp.u32 	%r972, 1, 0, %p134;
	add.s32 	%r973, %r972, %r944;
	st.local.u32 	[%r38+20], %r971;
	st.local.u32 	[%r38+24], %r973;
	and.b32  	%r202, %r201, 31;
	shl.b32 	%r975, %r952, 2;
	add.s32 	%r976, %r975, %r38;
	add.s32 	%r203, %r976, -16;
	ld.local.u32 	%r1755, [%r976+8];
	ld.local.u32 	%r1756, [%r976+4];
	setp.eq.s32 	%p135, %r202, 0;
	@%p135 bra 	BB13_139;

	shl.b32 	%r977, %r1755, %r202;
	neg.s32 	%r978, %r201;
	and.b32  	%r979, %r978, 31;
	shr.u32 	%r980, %r1756, %r979;
	or.b32  	%r1755, %r980, %r977;
	ld.local.u32 	%r981, [%r203+16];
	shr.u32 	%r982, %r981, %r979;
	shl.b32 	%r983, %r1756, %r202;
	or.b32  	%r1756, %r982, %r983;

BB13_139:
	shr.u32 	%r984, %r1756, 30;
	shl.b32 	%r985, %r1755, 2;
	or.b32  	%r1761, %r984, %r985;
	shl.b32 	%r211, %r1756, 2;
	setp.ne.s32 	%p136, %r211, 0;
	selp.u32 	%r986, 1, 0, %p136;
	add.s32 	%r987, %r986, %r1761;
	setp.gt.u32 	%p137, %r987, -2147483648;
	selp.u32 	%r988, 1, 0, %p137;
	shr.u32 	%r989, %r1755, 30;
	add.s32 	%r990, %r988, %r989;
	neg.s32 	%r991, %r990;
	setp.lt.s32 	%p138, %r199, 0;
	selp.b32 	%r1765, %r991, %r990, %p138;
	@%p137 bra 	BB13_141;

	mov.u32 	%r1760, %r211;
	bra.uni 	BB13_142;

BB13_141:
	not.b32 	%r992, %r1761;
	neg.s32 	%r213, %r211;
	setp.eq.s32 	%p139, %r211, 0;
	selp.u32 	%r993, 1, 0, %p139;
	add.s32 	%r1761, %r993, %r992;
	xor.b32  	%r1757, %r1757, -2147483648;
	mov.u32 	%r1760, %r213;

BB13_142:
	mov.u32 	%r1759, %r1760;
	setp.gt.s32 	%p140, %r1761, 0;
	@%p140 bra 	BB13_144;

	mov.u32 	%r1764, 0;
	bra.uni 	BB13_146;

BB13_144:
	mov.u32 	%r1764, 0;

BB13_145:
	shr.u32 	%r996, %r1759, 31;
	shl.b32 	%r997, %r1761, 1;
	or.b32  	%r1761, %r996, %r997;
	shl.b32 	%r1759, %r1759, 1;
	add.s32 	%r1764, %r1764, -1;
	setp.gt.s32 	%p141, %r1761, 0;
	@%p141 bra 	BB13_145;

BB13_146:
	mul.lo.s32 	%r1763, %r1761, -921707870;
	mov.u32 	%r1000, -921707870;
	// inline asm
	mul.hi.u32 	%r998, %r1761, %r1000;
	// inline asm
	setp.gt.s32 	%p142, %r998, 0;
	mov.u32 	%r1762, %r998;
	@%p142 bra 	BB13_147;
	bra.uni 	BB13_148;

BB13_147:
	shl.b32 	%r1001, %r998, 1;
	shr.u32 	%r1002, %r1763, 31;
	or.b32  	%r1762, %r1001, %r1002;
	mul.lo.s32 	%r1763, %r1761, -1843415740;
	add.s32 	%r1764, %r1764, -1;

BB13_148:
	setp.ne.s32 	%p143, %r1763, 0;
	selp.u32 	%r1003, 1, 0, %p143;
	add.s32 	%r1004, %r1003, %r1762;
	shr.u32 	%r1005, %r1004, 8;
	shr.u32 	%r1006, %r1004, 7;
	and.b32  	%r1007, %r1006, 1;
	shl.b32 	%r1008, %r1764, 23;
	add.s32 	%r1009, %r1008, %r1005;
	add.s32 	%r1010, %r1009, %r1007;
	add.s32 	%r1011, %r1010, 1056964608;
	or.b32  	%r1012, %r1011, %r1757;
	mov.b32 	 %f1062, %r1012;

BB13_149:
	add.s32 	%r236, %r1765, 1;
	and.b32  	%r1013, %r236, 1;
	setp.eq.s32 	%p144, %r1013, 0;
	mul.rn.f32 	%f82, %f1062, %f1062;
	@%p144 bra 	BB13_151;

	mov.f32 	%f457, 0f37CCF5CE;
	mul.rn.f32 	%f458, %f457, %f82;
	add.f32 	%f459, %f458, 0fBAB6061A;
	mul.rn.f32 	%f460, %f459, %f82;
	add.f32 	%f461, %f460, 0f3D2AAAA5;
	mul.rn.f32 	%f462, %f461, %f82;
	add.f32 	%f463, %f462, 0fBF000000;
	mul.rn.f32 	%f464, %f463, %f82;
	add.f32 	%f1063, %f464, 0f3F800000;
	bra.uni 	BB13_152;

BB13_151:
	mov.f32 	%f465, 0fB94CA1F9;
	mul.rn.f32 	%f466, %f465, %f82;
	add.f32 	%f467, %f466, 0f3C08839E;
	mul.rn.f32 	%f468, %f467, %f82;
	add.f32 	%f469, %f468, 0fBE2AAAA3;
	mul.rn.f32 	%f470, %f469, %f82;
	mul.rn.f32 	%f471, %f470, %f1062;
	add.f32 	%f1063, %f471, %f1062;

BB13_152:
	and.b32  	%r1014, %r236, 2;
	setp.eq.s32 	%p145, %r1014, 0;
	neg.f32 	%f472, %f1063;
	selp.f32 	%f1102, %f1063, %f472, %p145;
	bra.uni 	BB13_154;

BB13_153:
	mov.f32 	%f1102, %f14;

BB13_154:
	mad.f32 	%f88, %f1102, 0f3EEB851F, 0f3F0A3D71;
	mov.f32 	%f1068, %f88;
	bra.uni 	BB13_189;

BB13_155:
	mul.f32 	%f89, %f257, 0f40490FDC;
	setp.eq.f32 	%p146, %f89, %f12;
	setp.eq.f32 	%p147, %f89, %f13;
	or.pred  	%p148, %p146, %p147;
	@%p148 bra 	BB13_174;

	// inline asm
	abs.f32 	%f473, %f89;
	// inline asm
	setp.gt.f32 	%p149, %f473, 0f473BA700;
	@%p149 bra 	BB13_158;

	mov.f32 	%f477, 0f3F22F983;
	mul.rn.f32 	%f476, %f89, %f477;
	// inline asm
	cvt.rni.f32.f32 	%f475, %f476;
	// inline asm
	cvt.rzi.s32.f32 	%r1776, %f475;
	cvt.rn.f32.s32 	%f478, %r1776;
	mov.f32 	%f479, 0f3FC90000;
	mul.rn.f32 	%f480, %f478, %f479;
	sub.f32 	%f481, %f89, %f480;
	mov.f32 	%f482, 0f39FD8000;
	mul.rn.f32 	%f483, %f478, %f482;
	sub.f32 	%f484, %f481, %f483;
	mov.f32 	%f485, 0f34A88000;
	mul.rn.f32 	%f486, %f478, %f485;
	sub.f32 	%f487, %f484, %f486;
	mov.f32 	%f488, 0f2E85A309;
	mul.rn.f32 	%f489, %f478, %f488;
	sub.f32 	%f1064, %f487, %f489;
	bra.uni 	BB13_170;

BB13_158:
	mov.b32 	 %r238, %f89;
	and.b32  	%r1768, %r238, -2147483648;
	shr.u32 	%r240, %r238, 23;
	and.b32  	%r1033, %r240, 255;
	add.s32 	%r1034, %r1033, -128;
	shl.b32 	%r1035, %r238, 8;
	or.b32  	%r1032, %r1035, -2147483648;
	shr.u32 	%r1036, %r1034, 5;
	mov.u32 	%r1037, 4;
	sub.s32 	%r1038, %r1037, %r1036;
	ld.const.u32 	%r1016, [__GPU_i2opi_f];
	mul.lo.s32 	%r1039, %r1016, %r1032;
	// inline asm
	mul.hi.u32 	%r1015, %r1016, %r1032;
	// inline asm
	st.local.u32 	[%r38], %r1039;
	ld.const.u32 	%r1019, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1040, %r1019, %r1032;
	// inline asm
	mul.hi.u32 	%r1018, %r1019, %r1032;
	// inline asm
	mad.lo.s32 	%r1041, %r1019, %r1032, %r1015;
	setp.lt.u32 	%p150, %r1041, %r1040;
	selp.u32 	%r1042, 1, 0, %p150;
	add.s32 	%r1043, %r1042, %r1018;
	st.local.u32 	[%r38+4], %r1041;
	ld.const.u32 	%r1022, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1044, %r1022, %r1032;
	// inline asm
	mul.hi.u32 	%r1021, %r1022, %r1032;
	// inline asm
	mad.lo.s32 	%r1045, %r1022, %r1032, %r1043;
	setp.lt.u32 	%p151, %r1045, %r1044;
	selp.u32 	%r1046, 1, 0, %p151;
	add.s32 	%r1047, %r1046, %r1021;
	st.local.u32 	[%r38+8], %r1045;
	ld.const.u32 	%r1025, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1048, %r1025, %r1032;
	// inline asm
	mul.hi.u32 	%r1024, %r1025, %r1032;
	// inline asm
	mad.lo.s32 	%r1049, %r1025, %r1032, %r1047;
	setp.lt.u32 	%p152, %r1049, %r1048;
	selp.u32 	%r1050, 1, 0, %p152;
	add.s32 	%r1051, %r1050, %r1024;
	st.local.u32 	[%r38+12], %r1049;
	ld.const.u32 	%r1028, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1052, %r1028, %r1032;
	// inline asm
	mul.hi.u32 	%r1027, %r1028, %r1032;
	// inline asm
	mad.lo.s32 	%r1053, %r1028, %r1032, %r1051;
	setp.lt.u32 	%p153, %r1053, %r1052;
	selp.u32 	%r1054, 1, 0, %p153;
	add.s32 	%r1055, %r1054, %r1027;
	st.local.u32 	[%r38+16], %r1053;
	ld.const.u32 	%r1031, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1056, %r1031, %r1032;
	// inline asm
	mul.hi.u32 	%r1030, %r1031, %r1032;
	// inline asm
	mad.lo.s32 	%r1057, %r1031, %r1032, %r1055;
	setp.lt.u32 	%p154, %r1057, %r1056;
	selp.u32 	%r1058, 1, 0, %p154;
	add.s32 	%r1059, %r1058, %r1030;
	st.local.u32 	[%r38+20], %r1057;
	st.local.u32 	[%r38+24], %r1059;
	and.b32  	%r241, %r240, 31;
	shl.b32 	%r1061, %r1038, 2;
	add.s32 	%r1062, %r1061, %r38;
	add.s32 	%r242, %r1062, -16;
	ld.local.u32 	%r1766, [%r1062+8];
	ld.local.u32 	%r1767, [%r1062+4];
	setp.eq.s32 	%p155, %r241, 0;
	@%p155 bra 	BB13_160;

	shl.b32 	%r1063, %r1766, %r241;
	neg.s32 	%r1064, %r240;
	and.b32  	%r1065, %r1064, 31;
	shr.u32 	%r1066, %r1767, %r1065;
	or.b32  	%r1766, %r1066, %r1063;
	ld.local.u32 	%r1067, [%r242+16];
	shr.u32 	%r1068, %r1067, %r1065;
	shl.b32 	%r1069, %r1767, %r241;
	or.b32  	%r1767, %r1068, %r1069;

BB13_160:
	shr.u32 	%r1070, %r1767, 30;
	shl.b32 	%r1071, %r1766, 2;
	or.b32  	%r1772, %r1070, %r1071;
	shl.b32 	%r250, %r1767, 2;
	setp.ne.s32 	%p156, %r250, 0;
	selp.u32 	%r1072, 1, 0, %p156;
	add.s32 	%r1073, %r1072, %r1772;
	setp.gt.u32 	%p157, %r1073, -2147483648;
	selp.u32 	%r1074, 1, 0, %p157;
	shr.u32 	%r1075, %r1766, 30;
	add.s32 	%r1076, %r1074, %r1075;
	neg.s32 	%r1077, %r1076;
	setp.lt.s32 	%p158, %r238, 0;
	selp.b32 	%r1776, %r1077, %r1076, %p158;
	@%p157 bra 	BB13_162;

	mov.u32 	%r1771, %r250;
	bra.uni 	BB13_163;

BB13_162:
	not.b32 	%r1078, %r1772;
	neg.s32 	%r252, %r250;
	setp.eq.s32 	%p159, %r250, 0;
	selp.u32 	%r1079, 1, 0, %p159;
	add.s32 	%r1772, %r1079, %r1078;
	xor.b32  	%r1768, %r1768, -2147483648;
	mov.u32 	%r1771, %r252;

BB13_163:
	mov.u32 	%r1770, %r1771;
	setp.gt.s32 	%p160, %r1772, 0;
	@%p160 bra 	BB13_165;

	mov.u32 	%r1775, 0;
	bra.uni 	BB13_167;

BB13_165:
	mov.u32 	%r1775, 0;

BB13_166:
	shr.u32 	%r1082, %r1770, 31;
	shl.b32 	%r1083, %r1772, 1;
	or.b32  	%r1772, %r1082, %r1083;
	shl.b32 	%r1770, %r1770, 1;
	add.s32 	%r1775, %r1775, -1;
	setp.gt.s32 	%p161, %r1772, 0;
	@%p161 bra 	BB13_166;

BB13_167:
	mul.lo.s32 	%r1774, %r1772, -921707870;
	mov.u32 	%r1086, -921707870;
	// inline asm
	mul.hi.u32 	%r1084, %r1772, %r1086;
	// inline asm
	setp.gt.s32 	%p162, %r1084, 0;
	mov.u32 	%r1773, %r1084;
	@%p162 bra 	BB13_168;
	bra.uni 	BB13_169;

BB13_168:
	shl.b32 	%r1087, %r1084, 1;
	shr.u32 	%r1088, %r1774, 31;
	or.b32  	%r1773, %r1087, %r1088;
	mul.lo.s32 	%r1774, %r1772, -1843415740;
	add.s32 	%r1775, %r1775, -1;

BB13_169:
	setp.ne.s32 	%p163, %r1774, 0;
	selp.u32 	%r1089, 1, 0, %p163;
	add.s32 	%r1090, %r1089, %r1773;
	shr.u32 	%r1091, %r1090, 8;
	shr.u32 	%r1092, %r1090, 7;
	and.b32  	%r1093, %r1092, 1;
	shl.b32 	%r1094, %r1775, 23;
	add.s32 	%r1095, %r1094, %r1091;
	add.s32 	%r1096, %r1095, %r1093;
	add.s32 	%r1097, %r1096, 1056964608;
	or.b32  	%r1098, %r1097, %r1768;
	mov.b32 	 %f1064, %r1098;

BB13_170:
	add.s32 	%r275, %r1776, 1;
	and.b32  	%r1099, %r275, 1;
	setp.eq.s32 	%p164, %r1099, 0;
	mul.rn.f32 	%f93, %f1064, %f1064;
	@%p164 bra 	BB13_172;

	mov.f32 	%f490, 0f37CCF5CE;
	mul.rn.f32 	%f491, %f490, %f93;
	add.f32 	%f492, %f491, 0fBAB6061A;
	mul.rn.f32 	%f493, %f492, %f93;
	add.f32 	%f494, %f493, 0f3D2AAAA5;
	mul.rn.f32 	%f495, %f494, %f93;
	add.f32 	%f496, %f495, 0fBF000000;
	mul.rn.f32 	%f497, %f496, %f93;
	add.f32 	%f1065, %f497, 0f3F800000;
	bra.uni 	BB13_173;

BB13_172:
	mov.f32 	%f498, 0fB94CA1F9;
	mul.rn.f32 	%f499, %f498, %f93;
	add.f32 	%f500, %f499, 0f3C08839E;
	mul.rn.f32 	%f501, %f500, %f93;
	add.f32 	%f502, %f501, 0fBE2AAAA3;
	mul.rn.f32 	%f503, %f502, %f93;
	mul.rn.f32 	%f504, %f503, %f1064;
	add.f32 	%f1065, %f504, %f1064;

BB13_173:
	and.b32  	%r1100, %r275, 2;
	setp.eq.s32 	%p165, %r1100, 0;
	neg.f32 	%f505, %f1065;
	selp.f32 	%f1101, %f1065, %f505, %p165;
	bra.uni 	BB13_175;

BB13_174:
	mov.f32 	%f1101, %f14;

BB13_175:
	mad.f32 	%f99, %f1101, 0f3F000000, 0f3F000000;
	mov.f32 	%f1068, %f99;
	bra.uni 	BB13_189;

BB13_176:
	setp.lt.f32 	%p166, %f257, 0f3F800000;
	mov.f32 	%f506, 0f3F800000;
	sub.f32 	%f507, %f506, %f257;
	selp.f32 	%f100, %f507, 0f00000000, %p166;
	mov.f32 	%f1068, %f100;
	bra.uni 	BB13_189;

BB13_177:
	ld.param.u32 	%r1693, [ResizeVerticalFilter_param_10];
	ld.global.f32 	%f514, [%r1693];
	ld.global.f32 	%f515, [%r1693+8];
	ld.global.f32 	%f516, [%r1693+4];
	mad.f32 	%f517, %f257, %f515, %f516;
	mul.f32 	%f518, %f257, %f517;
	mad.f32 	%f102, %f257, %f518, %f514;
	mov.f32 	%f1068, %f102;
	bra.uni 	BB13_189;

BB13_178:
	setp.neu.f32 	%p169, %f257, 0f00000000;
	@%p169 bra 	BB13_180;

BB13_179:
	mov.f32 	%f1068, %f234;
	bra.uni 	BB13_189;

BB13_180:
	mul.f32 	%f103, %f257, 0f40490FDC;
	setp.eq.f32 	%p170, %f257, %f12;
	@%p170 bra 	BB13_186;

	setp.eq.f32 	%p171, %f257, %f13;
	setp.eq.f32 	%p172, %f257, 0f00000000;
	or.pred  	%p173, %p171, %p172;
	@%p173 bra 	BB13_186;

	mov.f32 	%f524, 0f40000000;
	mul.rn.f32 	%f521, %f524, %f257;
	// inline asm
	cvt.rni.f32.f32 	%f520, %f521;
	// inline asm
	cvt.rzi.s32.f32 	%r1101, %f520;
	neg.f32 	%f525, %f520;
	mul.rn.f32 	%f527, %f525, %f237;
	add.f32 	%f528, %f527, %f257;
	mov.f32 	%f529, 0f40490FDB;
	mul.rn.f32 	%f530, %f528, %f529;
	// inline asm
	abs.f32 	%f522, %f257;
	// inline asm
	setp.gt.f32 	%p174, %f522, 0f4B800000;
	selp.f32 	%f104, 0f00000000, %f530, %p174;
	selp.b32 	%r276, 0, %r1101, %p174;
	and.b32  	%r1102, %r276, 1;
	setp.eq.s32 	%p175, %r1102, 0;
	mul.rn.f32 	%f105, %f104, %f104;
	@%p175 bra 	BB13_184;

	mov.f32 	%f531, 0f37CCF5CE;
	mul.rn.f32 	%f532, %f531, %f105;
	add.f32 	%f533, %f532, 0fBAB6061A;
	mul.rn.f32 	%f534, %f533, %f105;
	add.f32 	%f535, %f534, 0f3D2AAAA5;
	mul.rn.f32 	%f536, %f535, %f105;
	add.f32 	%f537, %f536, 0fBF000000;
	mul.rn.f32 	%f538, %f537, %f105;
	add.f32 	%f1066, %f538, 0f3F800000;
	bra.uni 	BB13_185;

BB13_184:
	mov.f32 	%f539, 0fB94CA1F9;
	mul.rn.f32 	%f540, %f539, %f105;
	add.f32 	%f541, %f540, 0f3C08839E;
	mul.rn.f32 	%f542, %f541, %f105;
	add.f32 	%f543, %f542, 0fBE2AAAA3;
	mul.rn.f32 	%f544, %f543, %f105;
	mul.rn.f32 	%f545, %f544, %f104;
	add.f32 	%f1066, %f545, %f104;

BB13_185:
	and.b32  	%r1103, %r276, 2;
	setp.eq.s32 	%p176, %r1103, 0;
	neg.f32 	%f546, %f1066;
	selp.f32 	%f1067, %f1066, %f546, %p176;
	bra.uni 	BB13_187;

BB13_186:
	mov.f32 	%f547, 0f00000000;
	mul.rn.f32 	%f1067, %f257, %f547;

BB13_187:
	div.full.f32 	%f112, %f1067, %f103;
	mov.f32 	%f1068, %f112;
	bra.uni 	BB13_189;

BB13_188:
	mov.f32 	%f548, 0f00000000;
	mov.f32 	%f1068, %f548;

BB13_189:
	mov.f32 	%f113, %f1068;
	mul.f32 	%f549, %f1059, %f113;
	mul.f32 	%f550, %f549, 0f377BA882;
	mov.f32 	%f552, 0f477FFF00;
	sub.f32 	%f553, %f552, %f1030;
	mul.f32 	%f554, %f550, %f553;
	mad.f32 	%f557, %f554, %f1027, %f1124;
	mad.f32 	%f560, %f554, %f1028, %f1125;
	mad.f32 	%f563, %f554, %f1029, %f1126;
	mad.f32 	%f565, %f549, %f1030, %f1127;
	mov.f32 	%f1124, %f557;
	mov.f32 	%f1125, %f560;
	mov.f32 	%f1126, %f563;
	mov.f32 	%f1127, %f565;
	mad.f32 	%f1110, %f1059, %f113, %f1110;
	mad.f32 	%f1111, %f550, %f553, %f1111;
	add.s32 	%r1778, %r1778, 1;
	add.s32 	%r1777, %r1777, 1;
	setp.lt.u32 	%p177, %r1777, %r573;
	@%p177 bra 	BB13_12;
	bra.uni 	BB13_372;

BB13_190:
	@!%p3 bra 	BB13_371;

	mov.f32 	%f1110, 0f00000000;
	mov.f32 	%f1124, %f1110;
	mov.f32 	%f1125, %f1110;
	mov.f32 	%f1126, %f1110;
	mov.f32 	%f1127, %f1110;

BB13_192:
	shl.b32 	%r1104, %r1778, 4;
	ld.param.u32 	%r1697, [ResizeVerticalFilter_param_15];
	add.s32 	%r1105, %r1697, %r1104;
	ld.shared.v4.f32 	{%f1015, %f1016, %f1017, %f1018}, [%r1105];
	add.s32 	%r1106, %r1777, %r32;
	cvt.rn.f32.u32 	%f569, %r1106;
	sub.f32 	%f570, %f569, %f15;
	add.f32 	%f571, %f570, 0f3F000000;
	mul.f32 	%f572, %f1050, %f571;
	ld.param.f32 	%f1048, [ResizeVerticalFilter_param_14];
	div.full.f32 	%f568, %f572, %f1048;
	// inline asm
	abs.f32 	%f567, %f568;
	// inline asm
	@%p1 bra 	BB13_280;

	ld.param.f32 	%f1046, [ResizeVerticalFilter_param_11];
	mul.f32 	%f118, %f567, %f1046;
	ld.param.u32 	%r1678, [ResizeVerticalFilter_param_9];
	setp.gt.s32 	%p178, %r1678, 2;
	@%p178 bra 	BB13_200;

	ld.param.u32 	%r1672, [ResizeVerticalFilter_param_9];
	setp.eq.s32 	%p184, %r1672, 0;
	@%p184 bra 	BB13_280;

	ld.param.u32 	%r1671, [ResizeVerticalFilter_param_9];
	setp.eq.s32 	%p185, %r1671, 1;
	@%p185 bra 	BB13_268;

	ld.param.u32 	%r1670, [ResizeVerticalFilter_param_9];
	setp.eq.s32 	%p186, %r1670, 2;
	@%p186 bra 	BB13_197;
	bra.uni 	BB13_279;

BB13_197:
	setp.lt.f32 	%p248, %f118, 0f3F800000;
	@%p248 bra 	BB13_269;

	setp.geu.f32 	%p249, %f118, 0f40000000;
	@%p249 bra 	BB13_279;

	ld.param.u32 	%r1692, [ResizeVerticalFilter_param_10];
	ld.global.f32 	%f675, [%r1692+24];
	ld.global.f32 	%f676, [%r1692+20];
	mad.f32 	%f677, %f118, %f675, %f676;
	ld.global.f32 	%f678, [%r1692+16];
	mad.f32 	%f679, %f118, %f677, %f678;
	ld.global.f32 	%f680, [%r1692+12];
	mad.f32 	%f1077, %f118, %f679, %f680;
	bra.uni 	BB13_281;

BB13_200:
	ld.param.u32 	%r1677, [ResizeVerticalFilter_param_9];
	setp.gt.s32 	%p179, %r1677, 4;
	@%p179 bra 	BB13_206;

	ld.param.u32 	%r1674, [ResizeVerticalFilter_param_9];
	setp.eq.s32 	%p182, %r1674, 3;
	@%p182 bra 	BB13_247;

	ld.param.u32 	%r1673, [ResizeVerticalFilter_param_9];
	setp.eq.s32 	%p183, %r1673, 4;
	@%p183 bra 	BB13_203;
	bra.uni 	BB13_279;

BB13_203:
	mul.f32 	%f130, %f118, 0f40490FDC;
	setp.eq.f32 	%p207, %f130, %f12;
	setp.eq.f32 	%p208, %f130, %f13;
	or.pred  	%p209, %p207, %p208;
	@%p209 bra 	BB13_245;

	// inline asm
	abs.f32 	%f607, %f130;
	// inline asm
	setp.gt.f32 	%p210, %f607, 0f473BA700;
	@%p210 bra 	BB13_229;

	mov.f32 	%f611, 0f3F22F983;
	mul.rn.f32 	%f610, %f130, %f611;
	// inline asm
	cvt.rni.f32.f32 	%f609, %f610;
	// inline asm
	cvt.rzi.s32.f32 	%r1800, %f609;
	cvt.rn.f32.s32 	%f612, %r1800;
	mov.f32 	%f613, 0f3FC90000;
	mul.rn.f32 	%f614, %f612, %f613;
	sub.f32 	%f615, %f130, %f614;
	mov.f32 	%f616, 0f39FD8000;
	mul.rn.f32 	%f617, %f612, %f616;
	sub.f32 	%f618, %f615, %f617;
	mov.f32 	%f619, 0f34A88000;
	mul.rn.f32 	%f620, %f612, %f619;
	sub.f32 	%f621, %f618, %f620;
	mov.f32 	%f622, 0f2E85A309;
	mul.rn.f32 	%f623, %f612, %f622;
	sub.f32 	%f1071, %f621, %f623;
	bra.uni 	BB13_241;

BB13_206:
	ld.param.u32 	%r1676, [ResizeVerticalFilter_param_9];
	add.s32 	%r1107, %r1676, -9;
	setp.lt.u32 	%p180, %r1107, 2;
	@%p180 bra 	BB13_270;

	ld.param.u32 	%r1675, [ResizeVerticalFilter_param_9];
	setp.ne.s32 	%p181, %r1675, 5;
	@%p181 bra 	BB13_279;

	mul.f32 	%f119, %f118, 0f40490FDC;
	setp.eq.f32 	%p187, %f119, %f12;
	setp.eq.f32 	%p188, %f119, %f13;
	or.pred  	%p189, %p187, %p188;
	@%p189 bra 	BB13_227;

	// inline asm
	abs.f32 	%f573, %f119;
	// inline asm
	setp.gt.f32 	%p190, %f573, 0f473BA700;
	@%p190 bra 	BB13_211;

	mov.f32 	%f577, 0f3F22F983;
	mul.rn.f32 	%f576, %f119, %f577;
	// inline asm
	cvt.rni.f32.f32 	%f575, %f576;
	// inline asm
	cvt.rzi.s32.f32 	%r1789, %f575;
	cvt.rn.f32.s32 	%f578, %r1789;
	mov.f32 	%f579, 0f3FC90000;
	mul.rn.f32 	%f580, %f578, %f579;
	sub.f32 	%f581, %f119, %f580;
	mov.f32 	%f582, 0f39FD8000;
	mul.rn.f32 	%f583, %f578, %f582;
	sub.f32 	%f584, %f581, %f583;
	mov.f32 	%f585, 0f34A88000;
	mul.rn.f32 	%f586, %f578, %f585;
	sub.f32 	%f587, %f584, %f586;
	mov.f32 	%f588, 0f2E85A309;
	mul.rn.f32 	%f589, %f578, %f588;
	sub.f32 	%f1069, %f587, %f589;
	bra.uni 	BB13_223;

BB13_211:
	mov.b32 	 %r282, %f119;
	and.b32  	%r1781, %r282, -2147483648;
	shr.u32 	%r284, %r282, 23;
	and.b32  	%r1126, %r284, 255;
	add.s32 	%r1127, %r1126, -128;
	shl.b32 	%r1128, %r282, 8;
	or.b32  	%r1125, %r1128, -2147483648;
	shr.u32 	%r1129, %r1127, 5;
	mov.u32 	%r1130, 4;
	sub.s32 	%r1131, %r1130, %r1129;
	ld.const.u32 	%r1109, [__GPU_i2opi_f];
	mul.lo.s32 	%r1132, %r1109, %r1125;
	// inline asm
	mul.hi.u32 	%r1108, %r1109, %r1125;
	// inline asm
	st.local.u32 	[%r38], %r1132;
	ld.const.u32 	%r1112, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1133, %r1112, %r1125;
	// inline asm
	mul.hi.u32 	%r1111, %r1112, %r1125;
	// inline asm
	mad.lo.s32 	%r1134, %r1112, %r1125, %r1108;
	setp.lt.u32 	%p191, %r1134, %r1133;
	selp.u32 	%r1135, 1, 0, %p191;
	add.s32 	%r1136, %r1135, %r1111;
	st.local.u32 	[%r38+4], %r1134;
	ld.const.u32 	%r1115, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1137, %r1115, %r1125;
	// inline asm
	mul.hi.u32 	%r1114, %r1115, %r1125;
	// inline asm
	mad.lo.s32 	%r1138, %r1115, %r1125, %r1136;
	setp.lt.u32 	%p192, %r1138, %r1137;
	selp.u32 	%r1139, 1, 0, %p192;
	add.s32 	%r1140, %r1139, %r1114;
	st.local.u32 	[%r38+8], %r1138;
	ld.const.u32 	%r1118, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1141, %r1118, %r1125;
	// inline asm
	mul.hi.u32 	%r1117, %r1118, %r1125;
	// inline asm
	mad.lo.s32 	%r1142, %r1118, %r1125, %r1140;
	setp.lt.u32 	%p193, %r1142, %r1141;
	selp.u32 	%r1143, 1, 0, %p193;
	add.s32 	%r1144, %r1143, %r1117;
	st.local.u32 	[%r38+12], %r1142;
	ld.const.u32 	%r1121, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1145, %r1121, %r1125;
	// inline asm
	mul.hi.u32 	%r1120, %r1121, %r1125;
	// inline asm
	mad.lo.s32 	%r1146, %r1121, %r1125, %r1144;
	setp.lt.u32 	%p194, %r1146, %r1145;
	selp.u32 	%r1147, 1, 0, %p194;
	add.s32 	%r1148, %r1147, %r1120;
	st.local.u32 	[%r38+16], %r1146;
	ld.const.u32 	%r1124, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1149, %r1124, %r1125;
	// inline asm
	mul.hi.u32 	%r1123, %r1124, %r1125;
	// inline asm
	mad.lo.s32 	%r1150, %r1124, %r1125, %r1148;
	setp.lt.u32 	%p195, %r1150, %r1149;
	selp.u32 	%r1151, 1, 0, %p195;
	add.s32 	%r1152, %r1151, %r1123;
	st.local.u32 	[%r38+20], %r1150;
	st.local.u32 	[%r38+24], %r1152;
	and.b32  	%r285, %r284, 31;
	shl.b32 	%r1154, %r1131, 2;
	add.s32 	%r1155, %r1154, %r38;
	add.s32 	%r286, %r1155, -16;
	ld.local.u32 	%r1779, [%r1155+8];
	ld.local.u32 	%r1780, [%r1155+4];
	setp.eq.s32 	%p196, %r285, 0;
	@%p196 bra 	BB13_213;

	shl.b32 	%r1156, %r1779, %r285;
	neg.s32 	%r1157, %r284;
	and.b32  	%r1158, %r1157, 31;
	shr.u32 	%r1159, %r1780, %r1158;
	or.b32  	%r1779, %r1159, %r1156;
	ld.local.u32 	%r1160, [%r286+16];
	shr.u32 	%r1161, %r1160, %r1158;
	shl.b32 	%r1162, %r1780, %r285;
	or.b32  	%r1780, %r1161, %r1162;

BB13_213:
	shr.u32 	%r1163, %r1780, 30;
	shl.b32 	%r1164, %r1779, 2;
	or.b32  	%r1785, %r1163, %r1164;
	shl.b32 	%r294, %r1780, 2;
	setp.ne.s32 	%p197, %r294, 0;
	selp.u32 	%r1165, 1, 0, %p197;
	add.s32 	%r1166, %r1165, %r1785;
	setp.gt.u32 	%p198, %r1166, -2147483648;
	selp.u32 	%r1167, 1, 0, %p198;
	shr.u32 	%r1168, %r1779, 30;
	add.s32 	%r1169, %r1167, %r1168;
	neg.s32 	%r1170, %r1169;
	setp.lt.s32 	%p199, %r282, 0;
	selp.b32 	%r1789, %r1170, %r1169, %p199;
	@%p198 bra 	BB13_215;

	mov.u32 	%r1784, %r294;
	bra.uni 	BB13_216;

BB13_215:
	not.b32 	%r1171, %r1785;
	neg.s32 	%r296, %r294;
	setp.eq.s32 	%p200, %r294, 0;
	selp.u32 	%r1172, 1, 0, %p200;
	add.s32 	%r1785, %r1172, %r1171;
	xor.b32  	%r1781, %r1781, -2147483648;
	mov.u32 	%r1784, %r296;

BB13_216:
	mov.u32 	%r1783, %r1784;
	setp.gt.s32 	%p201, %r1785, 0;
	@%p201 bra 	BB13_218;

	mov.u32 	%r1788, 0;
	bra.uni 	BB13_220;

BB13_218:
	mov.u32 	%r1788, 0;

BB13_219:
	shr.u32 	%r1175, %r1783, 31;
	shl.b32 	%r1176, %r1785, 1;
	or.b32  	%r1785, %r1175, %r1176;
	shl.b32 	%r1783, %r1783, 1;
	add.s32 	%r1788, %r1788, -1;
	setp.gt.s32 	%p202, %r1785, 0;
	@%p202 bra 	BB13_219;

BB13_220:
	mul.lo.s32 	%r1787, %r1785, -921707870;
	mov.u32 	%r1179, -921707870;
	// inline asm
	mul.hi.u32 	%r1177, %r1785, %r1179;
	// inline asm
	setp.gt.s32 	%p203, %r1177, 0;
	mov.u32 	%r1786, %r1177;
	@%p203 bra 	BB13_221;
	bra.uni 	BB13_222;

BB13_221:
	shl.b32 	%r1180, %r1177, 1;
	shr.u32 	%r1181, %r1787, 31;
	or.b32  	%r1786, %r1180, %r1181;
	mul.lo.s32 	%r1787, %r1785, -1843415740;
	add.s32 	%r1788, %r1788, -1;

BB13_222:
	setp.ne.s32 	%p204, %r1787, 0;
	selp.u32 	%r1182, 1, 0, %p204;
	add.s32 	%r1183, %r1182, %r1786;
	shr.u32 	%r1184, %r1183, 8;
	shr.u32 	%r1185, %r1183, 7;
	and.b32  	%r1186, %r1185, 1;
	shl.b32 	%r1187, %r1788, 23;
	add.s32 	%r1188, %r1187, %r1184;
	add.s32 	%r1189, %r1188, %r1186;
	add.s32 	%r1190, %r1189, 1056964608;
	or.b32  	%r1191, %r1190, %r1781;
	mov.b32 	 %f1069, %r1191;

BB13_223:
	add.s32 	%r319, %r1789, 1;
	and.b32  	%r1192, %r319, 1;
	setp.eq.s32 	%p205, %r1192, 0;
	mul.rn.f32 	%f123, %f1069, %f1069;
	@%p205 bra 	BB13_225;

	mov.f32 	%f590, 0f37CCF5CE;
	mul.rn.f32 	%f591, %f590, %f123;
	add.f32 	%f592, %f591, 0fBAB6061A;
	mul.rn.f32 	%f593, %f592, %f123;
	add.f32 	%f594, %f593, 0f3D2AAAA5;
	mul.rn.f32 	%f595, %f594, %f123;
	add.f32 	%f596, %f595, 0fBF000000;
	mul.rn.f32 	%f597, %f596, %f123;
	add.f32 	%f1070, %f597, 0f3F800000;
	bra.uni 	BB13_226;

BB13_225:
	mov.f32 	%f598, 0fB94CA1F9;
	mul.rn.f32 	%f599, %f598, %f123;
	add.f32 	%f600, %f599, 0f3C08839E;
	mul.rn.f32 	%f601, %f600, %f123;
	add.f32 	%f602, %f601, 0fBE2AAAA3;
	mul.rn.f32 	%f603, %f602, %f123;
	mul.rn.f32 	%f604, %f603, %f1069;
	add.f32 	%f1070, %f604, %f1069;

BB13_226:
	and.b32  	%r1193, %r319, 2;
	setp.eq.s32 	%p206, %r1193, 0;
	neg.f32 	%f605, %f1070;
	selp.f32 	%f1100, %f1070, %f605, %p206;
	bra.uni 	BB13_228;

BB13_227:
	mov.f32 	%f1100, %f14;

BB13_228:
	mad.f32 	%f606, %f1100, 0f3E23D70A, 0f3F000000;
	mad.f32 	%f1077, %f1100, %f606, 0f3EAE147B;
	bra.uni 	BB13_281;

BB13_229:
	mov.b32 	 %r321, %f130;
	and.b32  	%r1792, %r321, -2147483648;
	shr.u32 	%r323, %r321, 23;
	and.b32  	%r1212, %r323, 255;
	add.s32 	%r1213, %r1212, -128;
	shl.b32 	%r1214, %r321, 8;
	or.b32  	%r1211, %r1214, -2147483648;
	shr.u32 	%r1215, %r1213, 5;
	mov.u32 	%r1216, 4;
	sub.s32 	%r1217, %r1216, %r1215;
	ld.const.u32 	%r1195, [__GPU_i2opi_f];
	mul.lo.s32 	%r1218, %r1195, %r1211;
	// inline asm
	mul.hi.u32 	%r1194, %r1195, %r1211;
	// inline asm
	st.local.u32 	[%r38], %r1218;
	ld.const.u32 	%r1198, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1219, %r1198, %r1211;
	// inline asm
	mul.hi.u32 	%r1197, %r1198, %r1211;
	// inline asm
	mad.lo.s32 	%r1220, %r1198, %r1211, %r1194;
	setp.lt.u32 	%p211, %r1220, %r1219;
	selp.u32 	%r1221, 1, 0, %p211;
	add.s32 	%r1222, %r1221, %r1197;
	st.local.u32 	[%r38+4], %r1220;
	ld.const.u32 	%r1201, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1223, %r1201, %r1211;
	// inline asm
	mul.hi.u32 	%r1200, %r1201, %r1211;
	// inline asm
	mad.lo.s32 	%r1224, %r1201, %r1211, %r1222;
	setp.lt.u32 	%p212, %r1224, %r1223;
	selp.u32 	%r1225, 1, 0, %p212;
	add.s32 	%r1226, %r1225, %r1200;
	st.local.u32 	[%r38+8], %r1224;
	ld.const.u32 	%r1204, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1227, %r1204, %r1211;
	// inline asm
	mul.hi.u32 	%r1203, %r1204, %r1211;
	// inline asm
	mad.lo.s32 	%r1228, %r1204, %r1211, %r1226;
	setp.lt.u32 	%p213, %r1228, %r1227;
	selp.u32 	%r1229, 1, 0, %p213;
	add.s32 	%r1230, %r1229, %r1203;
	st.local.u32 	[%r38+12], %r1228;
	ld.const.u32 	%r1207, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1231, %r1207, %r1211;
	// inline asm
	mul.hi.u32 	%r1206, %r1207, %r1211;
	// inline asm
	mad.lo.s32 	%r1232, %r1207, %r1211, %r1230;
	setp.lt.u32 	%p214, %r1232, %r1231;
	selp.u32 	%r1233, 1, 0, %p214;
	add.s32 	%r1234, %r1233, %r1206;
	st.local.u32 	[%r38+16], %r1232;
	ld.const.u32 	%r1210, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1235, %r1210, %r1211;
	// inline asm
	mul.hi.u32 	%r1209, %r1210, %r1211;
	// inline asm
	mad.lo.s32 	%r1236, %r1210, %r1211, %r1234;
	setp.lt.u32 	%p215, %r1236, %r1235;
	selp.u32 	%r1237, 1, 0, %p215;
	add.s32 	%r1238, %r1237, %r1209;
	st.local.u32 	[%r38+20], %r1236;
	st.local.u32 	[%r38+24], %r1238;
	and.b32  	%r324, %r323, 31;
	shl.b32 	%r1240, %r1217, 2;
	add.s32 	%r1241, %r1240, %r38;
	add.s32 	%r325, %r1241, -16;
	ld.local.u32 	%r1790, [%r1241+8];
	ld.local.u32 	%r1791, [%r1241+4];
	setp.eq.s32 	%p216, %r324, 0;
	@%p216 bra 	BB13_231;

	shl.b32 	%r1242, %r1790, %r324;
	neg.s32 	%r1243, %r323;
	and.b32  	%r1244, %r1243, 31;
	shr.u32 	%r1245, %r1791, %r1244;
	or.b32  	%r1790, %r1245, %r1242;
	ld.local.u32 	%r1246, [%r325+16];
	shr.u32 	%r1247, %r1246, %r1244;
	shl.b32 	%r1248, %r1791, %r324;
	or.b32  	%r1791, %r1247, %r1248;

BB13_231:
	shr.u32 	%r1249, %r1791, 30;
	shl.b32 	%r1250, %r1790, 2;
	or.b32  	%r1796, %r1249, %r1250;
	shl.b32 	%r333, %r1791, 2;
	setp.ne.s32 	%p217, %r333, 0;
	selp.u32 	%r1251, 1, 0, %p217;
	add.s32 	%r1252, %r1251, %r1796;
	setp.gt.u32 	%p218, %r1252, -2147483648;
	selp.u32 	%r1253, 1, 0, %p218;
	shr.u32 	%r1254, %r1790, 30;
	add.s32 	%r1255, %r1253, %r1254;
	neg.s32 	%r1256, %r1255;
	setp.lt.s32 	%p219, %r321, 0;
	selp.b32 	%r1800, %r1256, %r1255, %p219;
	@%p218 bra 	BB13_233;

	mov.u32 	%r1795, %r333;
	bra.uni 	BB13_234;

BB13_233:
	not.b32 	%r1257, %r1796;
	neg.s32 	%r335, %r333;
	setp.eq.s32 	%p220, %r333, 0;
	selp.u32 	%r1258, 1, 0, %p220;
	add.s32 	%r1796, %r1258, %r1257;
	xor.b32  	%r1792, %r1792, -2147483648;
	mov.u32 	%r1795, %r335;

BB13_234:
	mov.u32 	%r1794, %r1795;
	setp.gt.s32 	%p221, %r1796, 0;
	@%p221 bra 	BB13_236;

	mov.u32 	%r1799, 0;
	bra.uni 	BB13_238;

BB13_236:
	mov.u32 	%r1799, 0;

BB13_237:
	shr.u32 	%r1261, %r1794, 31;
	shl.b32 	%r1262, %r1796, 1;
	or.b32  	%r1796, %r1261, %r1262;
	shl.b32 	%r1794, %r1794, 1;
	add.s32 	%r1799, %r1799, -1;
	setp.gt.s32 	%p222, %r1796, 0;
	@%p222 bra 	BB13_237;

BB13_238:
	mul.lo.s32 	%r1798, %r1796, -921707870;
	mov.u32 	%r1265, -921707870;
	// inline asm
	mul.hi.u32 	%r1263, %r1796, %r1265;
	// inline asm
	setp.gt.s32 	%p223, %r1263, 0;
	mov.u32 	%r1797, %r1263;
	@%p223 bra 	BB13_239;
	bra.uni 	BB13_240;

BB13_239:
	shl.b32 	%r1266, %r1263, 1;
	shr.u32 	%r1267, %r1798, 31;
	or.b32  	%r1797, %r1266, %r1267;
	mul.lo.s32 	%r1798, %r1796, -1843415740;
	add.s32 	%r1799, %r1799, -1;

BB13_240:
	setp.ne.s32 	%p224, %r1798, 0;
	selp.u32 	%r1268, 1, 0, %p224;
	add.s32 	%r1269, %r1268, %r1797;
	shr.u32 	%r1270, %r1269, 8;
	shr.u32 	%r1271, %r1269, 7;
	and.b32  	%r1272, %r1271, 1;
	shl.b32 	%r1273, %r1799, 23;
	add.s32 	%r1274, %r1273, %r1270;
	add.s32 	%r1275, %r1274, %r1272;
	add.s32 	%r1276, %r1275, 1056964608;
	or.b32  	%r1277, %r1276, %r1792;
	mov.b32 	 %f1071, %r1277;

BB13_241:
	add.s32 	%r358, %r1800, 1;
	and.b32  	%r1278, %r358, 1;
	setp.eq.s32 	%p225, %r1278, 0;
	mul.rn.f32 	%f134, %f1071, %f1071;
	@%p225 bra 	BB13_243;

	mov.f32 	%f624, 0f37CCF5CE;
	mul.rn.f32 	%f625, %f624, %f134;
	add.f32 	%f626, %f625, 0fBAB6061A;
	mul.rn.f32 	%f627, %f626, %f134;
	add.f32 	%f628, %f627, 0f3D2AAAA5;
	mul.rn.f32 	%f629, %f628, %f134;
	add.f32 	%f630, %f629, 0fBF000000;
	mul.rn.f32 	%f631, %f630, %f134;
	add.f32 	%f1072, %f631, 0f3F800000;
	bra.uni 	BB13_244;

BB13_243:
	mov.f32 	%f632, 0fB94CA1F9;
	mul.rn.f32 	%f633, %f632, %f134;
	add.f32 	%f634, %f633, 0f3C08839E;
	mul.rn.f32 	%f635, %f634, %f134;
	add.f32 	%f636, %f635, 0fBE2AAAA3;
	mul.rn.f32 	%f637, %f636, %f134;
	mul.rn.f32 	%f638, %f637, %f1071;
	add.f32 	%f1072, %f638, %f1071;

BB13_244:
	and.b32  	%r1279, %r358, 2;
	setp.eq.s32 	%p226, %r1279, 0;
	neg.f32 	%f639, %f1072;
	selp.f32 	%f1099, %f1072, %f639, %p226;
	bra.uni 	BB13_246;

BB13_245:
	mov.f32 	%f1099, %f14;

BB13_246:
	mad.f32 	%f1077, %f1099, 0f3EEB851F, 0f3F0A3D71;
	bra.uni 	BB13_281;

BB13_247:
	mul.f32 	%f141, %f118, 0f40490FDC;
	setp.eq.f32 	%p227, %f141, %f12;
	setp.eq.f32 	%p228, %f141, %f13;
	or.pred  	%p229, %p227, %p228;
	@%p229 bra 	BB13_266;

	// inline asm
	abs.f32 	%f640, %f141;
	// inline asm
	setp.gt.f32 	%p230, %f640, 0f473BA700;
	@%p230 bra 	BB13_250;

	mov.f32 	%f644, 0f3F22F983;
	mul.rn.f32 	%f643, %f141, %f644;
	// inline asm
	cvt.rni.f32.f32 	%f642, %f643;
	// inline asm
	cvt.rzi.s32.f32 	%r1811, %f642;
	cvt.rn.f32.s32 	%f645, %r1811;
	mov.f32 	%f646, 0f3FC90000;
	mul.rn.f32 	%f647, %f645, %f646;
	sub.f32 	%f648, %f141, %f647;
	mov.f32 	%f649, 0f39FD8000;
	mul.rn.f32 	%f650, %f645, %f649;
	sub.f32 	%f651, %f648, %f650;
	mov.f32 	%f652, 0f34A88000;
	mul.rn.f32 	%f653, %f645, %f652;
	sub.f32 	%f654, %f651, %f653;
	mov.f32 	%f655, 0f2E85A309;
	mul.rn.f32 	%f656, %f645, %f655;
	sub.f32 	%f1073, %f654, %f656;
	bra.uni 	BB13_262;

BB13_250:
	mov.b32 	 %r360, %f141;
	and.b32  	%r1803, %r360, -2147483648;
	shr.u32 	%r362, %r360, 23;
	and.b32  	%r1298, %r362, 255;
	add.s32 	%r1299, %r1298, -128;
	shl.b32 	%r1300, %r360, 8;
	or.b32  	%r1297, %r1300, -2147483648;
	shr.u32 	%r1301, %r1299, 5;
	mov.u32 	%r1302, 4;
	sub.s32 	%r1303, %r1302, %r1301;
	ld.const.u32 	%r1281, [__GPU_i2opi_f];
	mul.lo.s32 	%r1304, %r1281, %r1297;
	// inline asm
	mul.hi.u32 	%r1280, %r1281, %r1297;
	// inline asm
	st.local.u32 	[%r38], %r1304;
	ld.const.u32 	%r1284, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1305, %r1284, %r1297;
	// inline asm
	mul.hi.u32 	%r1283, %r1284, %r1297;
	// inline asm
	mad.lo.s32 	%r1306, %r1284, %r1297, %r1280;
	setp.lt.u32 	%p231, %r1306, %r1305;
	selp.u32 	%r1307, 1, 0, %p231;
	add.s32 	%r1308, %r1307, %r1283;
	st.local.u32 	[%r38+4], %r1306;
	ld.const.u32 	%r1287, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1309, %r1287, %r1297;
	// inline asm
	mul.hi.u32 	%r1286, %r1287, %r1297;
	// inline asm
	mad.lo.s32 	%r1310, %r1287, %r1297, %r1308;
	setp.lt.u32 	%p232, %r1310, %r1309;
	selp.u32 	%r1311, 1, 0, %p232;
	add.s32 	%r1312, %r1311, %r1286;
	st.local.u32 	[%r38+8], %r1310;
	ld.const.u32 	%r1290, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1313, %r1290, %r1297;
	// inline asm
	mul.hi.u32 	%r1289, %r1290, %r1297;
	// inline asm
	mad.lo.s32 	%r1314, %r1290, %r1297, %r1312;
	setp.lt.u32 	%p233, %r1314, %r1313;
	selp.u32 	%r1315, 1, 0, %p233;
	add.s32 	%r1316, %r1315, %r1289;
	st.local.u32 	[%r38+12], %r1314;
	ld.const.u32 	%r1293, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1317, %r1293, %r1297;
	// inline asm
	mul.hi.u32 	%r1292, %r1293, %r1297;
	// inline asm
	mad.lo.s32 	%r1318, %r1293, %r1297, %r1316;
	setp.lt.u32 	%p234, %r1318, %r1317;
	selp.u32 	%r1319, 1, 0, %p234;
	add.s32 	%r1320, %r1319, %r1292;
	st.local.u32 	[%r38+16], %r1318;
	ld.const.u32 	%r1296, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1321, %r1296, %r1297;
	// inline asm
	mul.hi.u32 	%r1295, %r1296, %r1297;
	// inline asm
	mad.lo.s32 	%r1322, %r1296, %r1297, %r1320;
	setp.lt.u32 	%p235, %r1322, %r1321;
	selp.u32 	%r1323, 1, 0, %p235;
	add.s32 	%r1324, %r1323, %r1295;
	st.local.u32 	[%r38+20], %r1322;
	st.local.u32 	[%r38+24], %r1324;
	and.b32  	%r363, %r362, 31;
	shl.b32 	%r1326, %r1303, 2;
	add.s32 	%r1327, %r1326, %r38;
	add.s32 	%r364, %r1327, -16;
	ld.local.u32 	%r1801, [%r1327+8];
	ld.local.u32 	%r1802, [%r1327+4];
	setp.eq.s32 	%p236, %r363, 0;
	@%p236 bra 	BB13_252;

	shl.b32 	%r1328, %r1801, %r363;
	neg.s32 	%r1329, %r362;
	and.b32  	%r1330, %r1329, 31;
	shr.u32 	%r1331, %r1802, %r1330;
	or.b32  	%r1801, %r1331, %r1328;
	ld.local.u32 	%r1332, [%r364+16];
	shr.u32 	%r1333, %r1332, %r1330;
	shl.b32 	%r1334, %r1802, %r363;
	or.b32  	%r1802, %r1333, %r1334;

BB13_252:
	shr.u32 	%r1335, %r1802, 30;
	shl.b32 	%r1336, %r1801, 2;
	or.b32  	%r1807, %r1335, %r1336;
	shl.b32 	%r372, %r1802, 2;
	setp.ne.s32 	%p237, %r372, 0;
	selp.u32 	%r1337, 1, 0, %p237;
	add.s32 	%r1338, %r1337, %r1807;
	setp.gt.u32 	%p238, %r1338, -2147483648;
	selp.u32 	%r1339, 1, 0, %p238;
	shr.u32 	%r1340, %r1801, 30;
	add.s32 	%r1341, %r1339, %r1340;
	neg.s32 	%r1342, %r1341;
	setp.lt.s32 	%p239, %r360, 0;
	selp.b32 	%r1811, %r1342, %r1341, %p239;
	@%p238 bra 	BB13_254;

	mov.u32 	%r1806, %r372;
	bra.uni 	BB13_255;

BB13_254:
	not.b32 	%r1343, %r1807;
	neg.s32 	%r374, %r372;
	setp.eq.s32 	%p240, %r372, 0;
	selp.u32 	%r1344, 1, 0, %p240;
	add.s32 	%r1807, %r1344, %r1343;
	xor.b32  	%r1803, %r1803, -2147483648;
	mov.u32 	%r1806, %r374;

BB13_255:
	mov.u32 	%r1805, %r1806;
	setp.gt.s32 	%p241, %r1807, 0;
	@%p241 bra 	BB13_257;

	mov.u32 	%r1810, 0;
	bra.uni 	BB13_259;

BB13_257:
	mov.u32 	%r1810, 0;

BB13_258:
	shr.u32 	%r1347, %r1805, 31;
	shl.b32 	%r1348, %r1807, 1;
	or.b32  	%r1807, %r1347, %r1348;
	shl.b32 	%r1805, %r1805, 1;
	add.s32 	%r1810, %r1810, -1;
	setp.gt.s32 	%p242, %r1807, 0;
	@%p242 bra 	BB13_258;

BB13_259:
	mul.lo.s32 	%r1809, %r1807, -921707870;
	mov.u32 	%r1351, -921707870;
	// inline asm
	mul.hi.u32 	%r1349, %r1807, %r1351;
	// inline asm
	setp.gt.s32 	%p243, %r1349, 0;
	mov.u32 	%r1808, %r1349;
	@%p243 bra 	BB13_260;
	bra.uni 	BB13_261;

BB13_260:
	shl.b32 	%r1352, %r1349, 1;
	shr.u32 	%r1353, %r1809, 31;
	or.b32  	%r1808, %r1352, %r1353;
	mul.lo.s32 	%r1809, %r1807, -1843415740;
	add.s32 	%r1810, %r1810, -1;

BB13_261:
	setp.ne.s32 	%p244, %r1809, 0;
	selp.u32 	%r1354, 1, 0, %p244;
	add.s32 	%r1355, %r1354, %r1808;
	shr.u32 	%r1356, %r1355, 8;
	shr.u32 	%r1357, %r1355, 7;
	and.b32  	%r1358, %r1357, 1;
	shl.b32 	%r1359, %r1810, 23;
	add.s32 	%r1360, %r1359, %r1356;
	add.s32 	%r1361, %r1360, %r1358;
	add.s32 	%r1362, %r1361, 1056964608;
	or.b32  	%r1363, %r1362, %r1803;
	mov.b32 	 %f1073, %r1363;

BB13_262:
	add.s32 	%r397, %r1811, 1;
	and.b32  	%r1364, %r397, 1;
	setp.eq.s32 	%p245, %r1364, 0;
	mul.rn.f32 	%f145, %f1073, %f1073;
	@%p245 bra 	BB13_264;

	mov.f32 	%f657, 0f37CCF5CE;
	mul.rn.f32 	%f658, %f657, %f145;
	add.f32 	%f659, %f658, 0fBAB6061A;
	mul.rn.f32 	%f660, %f659, %f145;
	add.f32 	%f661, %f660, 0f3D2AAAA5;
	mul.rn.f32 	%f662, %f661, %f145;
	add.f32 	%f663, %f662, 0fBF000000;
	mul.rn.f32 	%f664, %f663, %f145;
	add.f32 	%f1074, %f664, 0f3F800000;
	bra.uni 	BB13_265;

BB13_264:
	mov.f32 	%f665, 0fB94CA1F9;
	mul.rn.f32 	%f666, %f665, %f145;
	add.f32 	%f667, %f666, 0f3C08839E;
	mul.rn.f32 	%f668, %f667, %f145;
	add.f32 	%f669, %f668, 0fBE2AAAA3;
	mul.rn.f32 	%f670, %f669, %f145;
	mul.rn.f32 	%f671, %f670, %f1073;
	add.f32 	%f1074, %f671, %f1073;

BB13_265:
	and.b32  	%r1365, %r397, 2;
	setp.eq.s32 	%p246, %r1365, 0;
	neg.f32 	%f672, %f1074;
	selp.f32 	%f1098, %f1074, %f672, %p246;
	bra.uni 	BB13_267;

BB13_266:
	mov.f32 	%f1098, %f14;

BB13_267:
	mad.f32 	%f1077, %f1098, 0f3F000000, 0f3F000000;
	bra.uni 	BB13_281;

BB13_268:
	setp.lt.f32 	%p247, %f118, 0f3F800000;
	mov.f32 	%f673, 0f3F800000;
	sub.f32 	%f674, %f673, %f118;
	selp.f32 	%f1077, %f674, 0f00000000, %p247;
	bra.uni 	BB13_281;

BB13_269:
	ld.param.u32 	%r1691, [ResizeVerticalFilter_param_10];
	ld.global.f32 	%f681, [%r1691];
	ld.global.f32 	%f682, [%r1691+8];
	ld.global.f32 	%f683, [%r1691+4];
	mad.f32 	%f684, %f118, %f682, %f683;
	mul.f32 	%f685, %f118, %f684;
	mad.f32 	%f1077, %f118, %f685, %f681;
	bra.uni 	BB13_281;

BB13_270:
	setp.eq.f32 	%p250, %f118, 0f00000000;
	@%p250 bra 	BB13_280;

	mul.f32 	%f155, %f118, 0f40490FDC;
	setp.eq.f32 	%p251, %f118, %f12;
	@%p251 bra 	BB13_277;

	setp.eq.f32 	%p252, %f118, %f13;
	or.pred  	%p254, %p252, %p250;
	@%p254 bra 	BB13_277;

	mov.f32 	%f690, 0f40000000;
	mul.rn.f32 	%f687, %f690, %f118;
	// inline asm
	cvt.rni.f32.f32 	%f686, %f687;
	// inline asm
	cvt.rzi.s32.f32 	%r1366, %f686;
	neg.f32 	%f691, %f686;
	mul.rn.f32 	%f693, %f691, %f237;
	add.f32 	%f694, %f693, %f118;
	mov.f32 	%f695, 0f40490FDB;
	mul.rn.f32 	%f696, %f694, %f695;
	// inline asm
	abs.f32 	%f688, %f118;
	// inline asm
	setp.gt.f32 	%p255, %f688, 0f4B800000;
	selp.f32 	%f156, 0f00000000, %f696, %p255;
	selp.b32 	%r398, 0, %r1366, %p255;
	and.b32  	%r1367, %r398, 1;
	setp.eq.s32 	%p256, %r1367, 0;
	mul.rn.f32 	%f157, %f156, %f156;
	@%p256 bra 	BB13_275;

	mov.f32 	%f697, 0f37CCF5CE;
	mul.rn.f32 	%f698, %f697, %f157;
	add.f32 	%f699, %f698, 0fBAB6061A;
	mul.rn.f32 	%f700, %f699, %f157;
	add.f32 	%f701, %f700, 0f3D2AAAA5;
	mul.rn.f32 	%f702, %f701, %f157;
	add.f32 	%f703, %f702, 0fBF000000;
	mul.rn.f32 	%f704, %f703, %f157;
	add.f32 	%f1075, %f704, 0f3F800000;
	bra.uni 	BB13_276;

BB13_275:
	mov.f32 	%f705, 0fB94CA1F9;
	mul.rn.f32 	%f706, %f705, %f157;
	add.f32 	%f707, %f706, 0f3C08839E;
	mul.rn.f32 	%f708, %f707, %f157;
	add.f32 	%f709, %f708, 0fBE2AAAA3;
	mul.rn.f32 	%f710, %f709, %f157;
	mul.rn.f32 	%f711, %f710, %f156;
	add.f32 	%f1075, %f711, %f156;

BB13_276:
	and.b32  	%r1368, %r398, 2;
	setp.eq.s32 	%p257, %r1368, 0;
	neg.f32 	%f712, %f1075;
	selp.f32 	%f1076, %f1075, %f712, %p257;
	bra.uni 	BB13_278;

BB13_277:
	mov.f32 	%f713, 0f00000000;
	mul.rn.f32 	%f1076, %f118, %f713;

BB13_278:
	div.full.f32 	%f1077, %f1076, %f155;
	bra.uni 	BB13_281;

BB13_279:
	mov.f32 	%f1077, 0f00000000;
	bra.uni 	BB13_281;

BB13_280:
	mov.f32 	%f1077, 0f3F800000;

BB13_281:
	ld.param.u32 	%r1660, [ResizeVerticalFilter_param_8];
	setp.gt.s32 	%p258, %r1660, 2;
	@%p258 bra 	BB13_288;

	ld.param.u32 	%r1654, [ResizeVerticalFilter_param_8];
	setp.eq.s32 	%p264, %r1654, 0;
	@%p264 bra 	BB13_359;

	ld.param.u32 	%r1653, [ResizeVerticalFilter_param_8];
	setp.eq.s32 	%p265, %r1653, 1;
	@%p265 bra 	BB13_356;

	ld.param.u32 	%r1652, [ResizeVerticalFilter_param_8];
	setp.eq.s32 	%p266, %r1652, 2;
	@%p266 bra 	BB13_285;
	bra.uni 	BB13_368;

BB13_285:
	setp.lt.f32 	%p328, %f567, 0f3F800000;
	@%p328 bra 	BB13_357;

	setp.geu.f32 	%p329, %f567, 0f40000000;
	@%p329 bra 	BB13_368;

	ld.param.u32 	%r1690, [ResizeVerticalFilter_param_10];
	ld.global.f32 	%f818, [%r1690+24];
	ld.global.f32 	%f819, [%r1690+20];
	mad.f32 	%f820, %f567, %f818, %f819;
	ld.global.f32 	%f821, [%r1690+16];
	mad.f32 	%f822, %f567, %f820, %f821;
	ld.global.f32 	%f823, [%r1690+12];
	mad.f32 	%f1109, %f567, %f822, %f823;
	bra.uni 	BB13_369;

BB13_288:
	ld.param.u32 	%r1659, [ResizeVerticalFilter_param_8];
	setp.gt.s32 	%p259, %r1659, 4;
	@%p259 bra 	BB13_294;

	ld.param.u32 	%r1656, [ResizeVerticalFilter_param_8];
	setp.eq.s32 	%p262, %r1656, 3;
	@%p262 bra 	BB13_335;

	ld.param.u32 	%r1655, [ResizeVerticalFilter_param_8];
	setp.eq.s32 	%p263, %r1655, 4;
	@%p263 bra 	BB13_291;
	bra.uni 	BB13_368;

BB13_291:
	mul.f32 	%f177, %f567, 0f40490FDC;
	setp.eq.f32 	%p287, %f177, %f12;
	setp.eq.f32 	%p288, %f177, %f13;
	or.pred  	%p289, %p287, %p288;
	@%p289 bra 	BB13_333;

	// inline asm
	abs.f32 	%f750, %f177;
	// inline asm
	setp.gt.f32 	%p290, %f750, 0f473BA700;
	@%p290 bra 	BB13_317;

	mov.f32 	%f754, 0f3F22F983;
	mul.rn.f32 	%f753, %f177, %f754;
	// inline asm
	cvt.rni.f32.f32 	%f752, %f753;
	// inline asm
	cvt.rzi.s32.f32 	%r1833, %f752;
	cvt.rn.f32.s32 	%f755, %r1833;
	mov.f32 	%f756, 0f3FC90000;
	mul.rn.f32 	%f757, %f755, %f756;
	sub.f32 	%f758, %f177, %f757;
	mov.f32 	%f759, 0f39FD8000;
	mul.rn.f32 	%f760, %f755, %f759;
	sub.f32 	%f761, %f758, %f760;
	mov.f32 	%f762, 0f34A88000;
	mul.rn.f32 	%f763, %f755, %f762;
	sub.f32 	%f764, %f761, %f763;
	mov.f32 	%f765, 0f2E85A309;
	mul.rn.f32 	%f766, %f755, %f765;
	sub.f32 	%f1080, %f764, %f766;
	bra.uni 	BB13_329;

BB13_294:
	ld.param.u32 	%r1658, [ResizeVerticalFilter_param_8];
	add.s32 	%r1369, %r1658, -9;
	setp.lt.u32 	%p260, %r1369, 2;
	@%p260 bra 	BB13_358;

	ld.param.u32 	%r1657, [ResizeVerticalFilter_param_8];
	setp.ne.s32 	%p261, %r1657, 5;
	@%p261 bra 	BB13_368;

	mul.f32 	%f166, %f567, 0f40490FDC;
	setp.eq.f32 	%p267, %f166, %f12;
	setp.eq.f32 	%p268, %f166, %f13;
	or.pred  	%p269, %p267, %p268;
	@%p269 bra 	BB13_315;

	// inline asm
	abs.f32 	%f716, %f166;
	// inline asm
	setp.gt.f32 	%p270, %f716, 0f473BA700;
	@%p270 bra 	BB13_299;

	mov.f32 	%f720, 0f3F22F983;
	mul.rn.f32 	%f719, %f166, %f720;
	// inline asm
	cvt.rni.f32.f32 	%f718, %f719;
	// inline asm
	cvt.rzi.s32.f32 	%r1822, %f718;
	cvt.rn.f32.s32 	%f721, %r1822;
	mov.f32 	%f722, 0f3FC90000;
	mul.rn.f32 	%f723, %f721, %f722;
	sub.f32 	%f724, %f166, %f723;
	mov.f32 	%f725, 0f39FD8000;
	mul.rn.f32 	%f726, %f721, %f725;
	sub.f32 	%f727, %f724, %f726;
	mov.f32 	%f728, 0f34A88000;
	mul.rn.f32 	%f729, %f721, %f728;
	sub.f32 	%f730, %f727, %f729;
	mov.f32 	%f731, 0f2E85A309;
	mul.rn.f32 	%f732, %f721, %f731;
	sub.f32 	%f1078, %f730, %f732;
	bra.uni 	BB13_311;

BB13_299:
	mov.b32 	 %r400, %f166;
	and.b32  	%r1814, %r400, -2147483648;
	shr.u32 	%r402, %r400, 23;
	and.b32  	%r1388, %r402, 255;
	add.s32 	%r1389, %r1388, -128;
	shl.b32 	%r1390, %r400, 8;
	or.b32  	%r1387, %r1390, -2147483648;
	shr.u32 	%r1391, %r1389, 5;
	mov.u32 	%r1392, 4;
	sub.s32 	%r1393, %r1392, %r1391;
	ld.const.u32 	%r1371, [__GPU_i2opi_f];
	mul.lo.s32 	%r1394, %r1371, %r1387;
	// inline asm
	mul.hi.u32 	%r1370, %r1371, %r1387;
	// inline asm
	st.local.u32 	[%r38], %r1394;
	ld.const.u32 	%r1374, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1395, %r1374, %r1387;
	// inline asm
	mul.hi.u32 	%r1373, %r1374, %r1387;
	// inline asm
	mad.lo.s32 	%r1396, %r1374, %r1387, %r1370;
	setp.lt.u32 	%p271, %r1396, %r1395;
	selp.u32 	%r1397, 1, 0, %p271;
	add.s32 	%r1398, %r1397, %r1373;
	st.local.u32 	[%r38+4], %r1396;
	ld.const.u32 	%r1377, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1399, %r1377, %r1387;
	// inline asm
	mul.hi.u32 	%r1376, %r1377, %r1387;
	// inline asm
	mad.lo.s32 	%r1400, %r1377, %r1387, %r1398;
	setp.lt.u32 	%p272, %r1400, %r1399;
	selp.u32 	%r1401, 1, 0, %p272;
	add.s32 	%r1402, %r1401, %r1376;
	st.local.u32 	[%r38+8], %r1400;
	ld.const.u32 	%r1380, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1403, %r1380, %r1387;
	// inline asm
	mul.hi.u32 	%r1379, %r1380, %r1387;
	// inline asm
	mad.lo.s32 	%r1404, %r1380, %r1387, %r1402;
	setp.lt.u32 	%p273, %r1404, %r1403;
	selp.u32 	%r1405, 1, 0, %p273;
	add.s32 	%r1406, %r1405, %r1379;
	st.local.u32 	[%r38+12], %r1404;
	ld.const.u32 	%r1383, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1407, %r1383, %r1387;
	// inline asm
	mul.hi.u32 	%r1382, %r1383, %r1387;
	// inline asm
	mad.lo.s32 	%r1408, %r1383, %r1387, %r1406;
	setp.lt.u32 	%p274, %r1408, %r1407;
	selp.u32 	%r1409, 1, 0, %p274;
	add.s32 	%r1410, %r1409, %r1382;
	st.local.u32 	[%r38+16], %r1408;
	ld.const.u32 	%r1386, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1411, %r1386, %r1387;
	// inline asm
	mul.hi.u32 	%r1385, %r1386, %r1387;
	// inline asm
	mad.lo.s32 	%r1412, %r1386, %r1387, %r1410;
	setp.lt.u32 	%p275, %r1412, %r1411;
	selp.u32 	%r1413, 1, 0, %p275;
	add.s32 	%r1414, %r1413, %r1385;
	st.local.u32 	[%r38+20], %r1412;
	st.local.u32 	[%r38+24], %r1414;
	and.b32  	%r403, %r402, 31;
	shl.b32 	%r1416, %r1393, 2;
	add.s32 	%r1417, %r1416, %r38;
	add.s32 	%r404, %r1417, -16;
	ld.local.u32 	%r1812, [%r1417+8];
	ld.local.u32 	%r1813, [%r1417+4];
	setp.eq.s32 	%p276, %r403, 0;
	@%p276 bra 	BB13_301;

	shl.b32 	%r1418, %r1812, %r403;
	neg.s32 	%r1419, %r402;
	and.b32  	%r1420, %r1419, 31;
	shr.u32 	%r1421, %r1813, %r1420;
	or.b32  	%r1812, %r1421, %r1418;
	ld.local.u32 	%r1422, [%r404+16];
	shr.u32 	%r1423, %r1422, %r1420;
	shl.b32 	%r1424, %r1813, %r403;
	or.b32  	%r1813, %r1423, %r1424;

BB13_301:
	shr.u32 	%r1425, %r1813, 30;
	shl.b32 	%r1426, %r1812, 2;
	or.b32  	%r1818, %r1425, %r1426;
	shl.b32 	%r412, %r1813, 2;
	setp.ne.s32 	%p277, %r412, 0;
	selp.u32 	%r1427, 1, 0, %p277;
	add.s32 	%r1428, %r1427, %r1818;
	setp.gt.u32 	%p278, %r1428, -2147483648;
	selp.u32 	%r1429, 1, 0, %p278;
	shr.u32 	%r1430, %r1812, 30;
	add.s32 	%r1431, %r1429, %r1430;
	neg.s32 	%r1432, %r1431;
	setp.lt.s32 	%p279, %r400, 0;
	selp.b32 	%r1822, %r1432, %r1431, %p279;
	@%p278 bra 	BB13_303;

	mov.u32 	%r1817, %r412;
	bra.uni 	BB13_304;

BB13_303:
	not.b32 	%r1433, %r1818;
	neg.s32 	%r414, %r412;
	setp.eq.s32 	%p280, %r412, 0;
	selp.u32 	%r1434, 1, 0, %p280;
	add.s32 	%r1818, %r1434, %r1433;
	xor.b32  	%r1814, %r1814, -2147483648;
	mov.u32 	%r1817, %r414;

BB13_304:
	mov.u32 	%r1816, %r1817;
	setp.gt.s32 	%p281, %r1818, 0;
	@%p281 bra 	BB13_306;

	mov.u32 	%r1821, 0;
	bra.uni 	BB13_308;

BB13_306:
	mov.u32 	%r1821, 0;

BB13_307:
	shr.u32 	%r1437, %r1816, 31;
	shl.b32 	%r1438, %r1818, 1;
	or.b32  	%r1818, %r1437, %r1438;
	shl.b32 	%r1816, %r1816, 1;
	add.s32 	%r1821, %r1821, -1;
	setp.gt.s32 	%p282, %r1818, 0;
	@%p282 bra 	BB13_307;

BB13_308:
	mul.lo.s32 	%r1820, %r1818, -921707870;
	mov.u32 	%r1441, -921707870;
	// inline asm
	mul.hi.u32 	%r1439, %r1818, %r1441;
	// inline asm
	setp.gt.s32 	%p283, %r1439, 0;
	mov.u32 	%r1819, %r1439;
	@%p283 bra 	BB13_309;
	bra.uni 	BB13_310;

BB13_309:
	shl.b32 	%r1442, %r1439, 1;
	shr.u32 	%r1443, %r1820, 31;
	or.b32  	%r1819, %r1442, %r1443;
	mul.lo.s32 	%r1820, %r1818, -1843415740;
	add.s32 	%r1821, %r1821, -1;

BB13_310:
	setp.ne.s32 	%p284, %r1820, 0;
	selp.u32 	%r1444, 1, 0, %p284;
	add.s32 	%r1445, %r1444, %r1819;
	shr.u32 	%r1446, %r1445, 8;
	shr.u32 	%r1447, %r1445, 7;
	and.b32  	%r1448, %r1447, 1;
	shl.b32 	%r1449, %r1821, 23;
	add.s32 	%r1450, %r1449, %r1446;
	add.s32 	%r1451, %r1450, %r1448;
	add.s32 	%r1452, %r1451, 1056964608;
	or.b32  	%r1453, %r1452, %r1814;
	mov.b32 	 %f1078, %r1453;

BB13_311:
	add.s32 	%r437, %r1822, 1;
	and.b32  	%r1454, %r437, 1;
	setp.eq.s32 	%p285, %r1454, 0;
	mul.rn.f32 	%f170, %f1078, %f1078;
	@%p285 bra 	BB13_313;

	mov.f32 	%f733, 0f37CCF5CE;
	mul.rn.f32 	%f734, %f733, %f170;
	add.f32 	%f735, %f734, 0fBAB6061A;
	mul.rn.f32 	%f736, %f735, %f170;
	add.f32 	%f737, %f736, 0f3D2AAAA5;
	mul.rn.f32 	%f738, %f737, %f170;
	add.f32 	%f739, %f738, 0fBF000000;
	mul.rn.f32 	%f740, %f739, %f170;
	add.f32 	%f1079, %f740, 0f3F800000;
	bra.uni 	BB13_314;

BB13_313:
	mov.f32 	%f741, 0fB94CA1F9;
	mul.rn.f32 	%f742, %f741, %f170;
	add.f32 	%f743, %f742, 0f3C08839E;
	mul.rn.f32 	%f744, %f743, %f170;
	add.f32 	%f745, %f744, 0fBE2AAAA3;
	mul.rn.f32 	%f746, %f745, %f170;
	mul.rn.f32 	%f747, %f746, %f1078;
	add.f32 	%f1079, %f747, %f1078;

BB13_314:
	and.b32  	%r1455, %r437, 2;
	setp.eq.s32 	%p286, %r1455, 0;
	neg.f32 	%f748, %f1079;
	selp.f32 	%f1097, %f1079, %f748, %p286;
	bra.uni 	BB13_316;

BB13_315:
	mov.f32 	%f1097, %f14;

BB13_316:
	mad.f32 	%f749, %f1097, 0f3E23D70A, 0f3F000000;
	mad.f32 	%f1109, %f1097, %f749, 0f3EAE147B;
	bra.uni 	BB13_369;

BB13_317:
	mov.b32 	 %r439, %f177;
	and.b32  	%r1825, %r439, -2147483648;
	shr.u32 	%r441, %r439, 23;
	and.b32  	%r1474, %r441, 255;
	add.s32 	%r1475, %r1474, -128;
	shl.b32 	%r1476, %r439, 8;
	or.b32  	%r1473, %r1476, -2147483648;
	shr.u32 	%r1477, %r1475, 5;
	mov.u32 	%r1478, 4;
	sub.s32 	%r1479, %r1478, %r1477;
	ld.const.u32 	%r1457, [__GPU_i2opi_f];
	mul.lo.s32 	%r1480, %r1457, %r1473;
	// inline asm
	mul.hi.u32 	%r1456, %r1457, %r1473;
	// inline asm
	st.local.u32 	[%r38], %r1480;
	ld.const.u32 	%r1460, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1481, %r1460, %r1473;
	// inline asm
	mul.hi.u32 	%r1459, %r1460, %r1473;
	// inline asm
	mad.lo.s32 	%r1482, %r1460, %r1473, %r1456;
	setp.lt.u32 	%p291, %r1482, %r1481;
	selp.u32 	%r1483, 1, 0, %p291;
	add.s32 	%r1484, %r1483, %r1459;
	st.local.u32 	[%r38+4], %r1482;
	ld.const.u32 	%r1463, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1485, %r1463, %r1473;
	// inline asm
	mul.hi.u32 	%r1462, %r1463, %r1473;
	// inline asm
	mad.lo.s32 	%r1486, %r1463, %r1473, %r1484;
	setp.lt.u32 	%p292, %r1486, %r1485;
	selp.u32 	%r1487, 1, 0, %p292;
	add.s32 	%r1488, %r1487, %r1462;
	st.local.u32 	[%r38+8], %r1486;
	ld.const.u32 	%r1466, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1489, %r1466, %r1473;
	// inline asm
	mul.hi.u32 	%r1465, %r1466, %r1473;
	// inline asm
	mad.lo.s32 	%r1490, %r1466, %r1473, %r1488;
	setp.lt.u32 	%p293, %r1490, %r1489;
	selp.u32 	%r1491, 1, 0, %p293;
	add.s32 	%r1492, %r1491, %r1465;
	st.local.u32 	[%r38+12], %r1490;
	ld.const.u32 	%r1469, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1493, %r1469, %r1473;
	// inline asm
	mul.hi.u32 	%r1468, %r1469, %r1473;
	// inline asm
	mad.lo.s32 	%r1494, %r1469, %r1473, %r1492;
	setp.lt.u32 	%p294, %r1494, %r1493;
	selp.u32 	%r1495, 1, 0, %p294;
	add.s32 	%r1496, %r1495, %r1468;
	st.local.u32 	[%r38+16], %r1494;
	ld.const.u32 	%r1472, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1497, %r1472, %r1473;
	// inline asm
	mul.hi.u32 	%r1471, %r1472, %r1473;
	// inline asm
	mad.lo.s32 	%r1498, %r1472, %r1473, %r1496;
	setp.lt.u32 	%p295, %r1498, %r1497;
	selp.u32 	%r1499, 1, 0, %p295;
	add.s32 	%r1500, %r1499, %r1471;
	st.local.u32 	[%r38+20], %r1498;
	st.local.u32 	[%r38+24], %r1500;
	and.b32  	%r442, %r441, 31;
	shl.b32 	%r1502, %r1479, 2;
	add.s32 	%r1503, %r1502, %r38;
	add.s32 	%r443, %r1503, -16;
	ld.local.u32 	%r1823, [%r1503+8];
	ld.local.u32 	%r1824, [%r1503+4];
	setp.eq.s32 	%p296, %r442, 0;
	@%p296 bra 	BB13_319;

	shl.b32 	%r1504, %r1823, %r442;
	neg.s32 	%r1505, %r441;
	and.b32  	%r1506, %r1505, 31;
	shr.u32 	%r1507, %r1824, %r1506;
	or.b32  	%r1823, %r1507, %r1504;
	ld.local.u32 	%r1508, [%r443+16];
	shr.u32 	%r1509, %r1508, %r1506;
	shl.b32 	%r1510, %r1824, %r442;
	or.b32  	%r1824, %r1509, %r1510;

BB13_319:
	shr.u32 	%r1511, %r1824, 30;
	shl.b32 	%r1512, %r1823, 2;
	or.b32  	%r1829, %r1511, %r1512;
	shl.b32 	%r451, %r1824, 2;
	setp.ne.s32 	%p297, %r451, 0;
	selp.u32 	%r1513, 1, 0, %p297;
	add.s32 	%r1514, %r1513, %r1829;
	setp.gt.u32 	%p298, %r1514, -2147483648;
	selp.u32 	%r1515, 1, 0, %p298;
	shr.u32 	%r1516, %r1823, 30;
	add.s32 	%r1517, %r1515, %r1516;
	neg.s32 	%r1518, %r1517;
	setp.lt.s32 	%p299, %r439, 0;
	selp.b32 	%r1833, %r1518, %r1517, %p299;
	@%p298 bra 	BB13_321;

	mov.u32 	%r1828, %r451;
	bra.uni 	BB13_322;

BB13_321:
	not.b32 	%r1519, %r1829;
	neg.s32 	%r453, %r451;
	setp.eq.s32 	%p300, %r451, 0;
	selp.u32 	%r1520, 1, 0, %p300;
	add.s32 	%r1829, %r1520, %r1519;
	xor.b32  	%r1825, %r1825, -2147483648;
	mov.u32 	%r1828, %r453;

BB13_322:
	mov.u32 	%r1827, %r1828;
	setp.gt.s32 	%p301, %r1829, 0;
	@%p301 bra 	BB13_324;

	mov.u32 	%r1832, 0;
	bra.uni 	BB13_326;

BB13_324:
	mov.u32 	%r1832, 0;

BB13_325:
	shr.u32 	%r1523, %r1827, 31;
	shl.b32 	%r1524, %r1829, 1;
	or.b32  	%r1829, %r1523, %r1524;
	shl.b32 	%r1827, %r1827, 1;
	add.s32 	%r1832, %r1832, -1;
	setp.gt.s32 	%p302, %r1829, 0;
	@%p302 bra 	BB13_325;

BB13_326:
	mul.lo.s32 	%r1831, %r1829, -921707870;
	mov.u32 	%r1527, -921707870;
	// inline asm
	mul.hi.u32 	%r1525, %r1829, %r1527;
	// inline asm
	setp.gt.s32 	%p303, %r1525, 0;
	mov.u32 	%r1830, %r1525;
	@%p303 bra 	BB13_327;
	bra.uni 	BB13_328;

BB13_327:
	shl.b32 	%r1528, %r1525, 1;
	shr.u32 	%r1529, %r1831, 31;
	or.b32  	%r1830, %r1528, %r1529;
	mul.lo.s32 	%r1831, %r1829, -1843415740;
	add.s32 	%r1832, %r1832, -1;

BB13_328:
	setp.ne.s32 	%p304, %r1831, 0;
	selp.u32 	%r1530, 1, 0, %p304;
	add.s32 	%r1531, %r1530, %r1830;
	shr.u32 	%r1532, %r1531, 8;
	shr.u32 	%r1533, %r1531, 7;
	and.b32  	%r1534, %r1533, 1;
	shl.b32 	%r1535, %r1832, 23;
	add.s32 	%r1536, %r1535, %r1532;
	add.s32 	%r1537, %r1536, %r1534;
	add.s32 	%r1538, %r1537, 1056964608;
	or.b32  	%r1539, %r1538, %r1825;
	mov.b32 	 %f1080, %r1539;

BB13_329:
	add.s32 	%r476, %r1833, 1;
	and.b32  	%r1540, %r476, 1;
	setp.eq.s32 	%p305, %r1540, 0;
	mul.rn.f32 	%f181, %f1080, %f1080;
	@%p305 bra 	BB13_331;

	mov.f32 	%f767, 0f37CCF5CE;
	mul.rn.f32 	%f768, %f767, %f181;
	add.f32 	%f769, %f768, 0fBAB6061A;
	mul.rn.f32 	%f770, %f769, %f181;
	add.f32 	%f771, %f770, 0f3D2AAAA5;
	mul.rn.f32 	%f772, %f771, %f181;
	add.f32 	%f773, %f772, 0fBF000000;
	mul.rn.f32 	%f774, %f773, %f181;
	add.f32 	%f1081, %f774, 0f3F800000;
	bra.uni 	BB13_332;

BB13_331:
	mov.f32 	%f775, 0fB94CA1F9;
	mul.rn.f32 	%f776, %f775, %f181;
	add.f32 	%f777, %f776, 0f3C08839E;
	mul.rn.f32 	%f778, %f777, %f181;
	add.f32 	%f779, %f778, 0fBE2AAAA3;
	mul.rn.f32 	%f780, %f779, %f181;
	mul.rn.f32 	%f781, %f780, %f1080;
	add.f32 	%f1081, %f781, %f1080;

BB13_332:
	and.b32  	%r1541, %r476, 2;
	setp.eq.s32 	%p306, %r1541, 0;
	neg.f32 	%f782, %f1081;
	selp.f32 	%f1096, %f1081, %f782, %p306;
	bra.uni 	BB13_334;

BB13_333:
	mov.f32 	%f1096, %f14;

BB13_334:
	mad.f32 	%f1109, %f1096, 0f3EEB851F, 0f3F0A3D71;
	bra.uni 	BB13_369;

BB13_335:
	mul.f32 	%f188, %f567, 0f40490FDC;
	setp.eq.f32 	%p307, %f188, %f12;
	setp.eq.f32 	%p308, %f188, %f13;
	or.pred  	%p309, %p307, %p308;
	@%p309 bra 	BB13_354;

	// inline asm
	abs.f32 	%f783, %f188;
	// inline asm
	setp.gt.f32 	%p310, %f783, 0f473BA700;
	@%p310 bra 	BB13_338;

	mov.f32 	%f787, 0f3F22F983;
	mul.rn.f32 	%f786, %f188, %f787;
	// inline asm
	cvt.rni.f32.f32 	%f785, %f786;
	// inline asm
	cvt.rzi.s32.f32 	%r1844, %f785;
	cvt.rn.f32.s32 	%f788, %r1844;
	mov.f32 	%f789, 0f3FC90000;
	mul.rn.f32 	%f790, %f788, %f789;
	sub.f32 	%f791, %f188, %f790;
	mov.f32 	%f792, 0f39FD8000;
	mul.rn.f32 	%f793, %f788, %f792;
	sub.f32 	%f794, %f791, %f793;
	mov.f32 	%f795, 0f34A88000;
	mul.rn.f32 	%f796, %f788, %f795;
	sub.f32 	%f797, %f794, %f796;
	mov.f32 	%f798, 0f2E85A309;
	mul.rn.f32 	%f799, %f788, %f798;
	sub.f32 	%f1082, %f797, %f799;
	bra.uni 	BB13_350;

BB13_338:
	mov.b32 	 %r478, %f188;
	and.b32  	%r1836, %r478, -2147483648;
	shr.u32 	%r480, %r478, 23;
	and.b32  	%r1560, %r480, 255;
	add.s32 	%r1561, %r1560, -128;
	shl.b32 	%r1562, %r478, 8;
	or.b32  	%r1559, %r1562, -2147483648;
	shr.u32 	%r1563, %r1561, 5;
	mov.u32 	%r1564, 4;
	sub.s32 	%r1565, %r1564, %r1563;
	ld.const.u32 	%r1543, [__GPU_i2opi_f];
	mul.lo.s32 	%r1566, %r1543, %r1559;
	// inline asm
	mul.hi.u32 	%r1542, %r1543, %r1559;
	// inline asm
	st.local.u32 	[%r38], %r1566;
	ld.const.u32 	%r1546, [__GPU_i2opi_f+4];
	mul.lo.s32 	%r1567, %r1546, %r1559;
	// inline asm
	mul.hi.u32 	%r1545, %r1546, %r1559;
	// inline asm
	mad.lo.s32 	%r1568, %r1546, %r1559, %r1542;
	setp.lt.u32 	%p311, %r1568, %r1567;
	selp.u32 	%r1569, 1, 0, %p311;
	add.s32 	%r1570, %r1569, %r1545;
	st.local.u32 	[%r38+4], %r1568;
	ld.const.u32 	%r1549, [__GPU_i2opi_f+8];
	mul.lo.s32 	%r1571, %r1549, %r1559;
	// inline asm
	mul.hi.u32 	%r1548, %r1549, %r1559;
	// inline asm
	mad.lo.s32 	%r1572, %r1549, %r1559, %r1570;
	setp.lt.u32 	%p312, %r1572, %r1571;
	selp.u32 	%r1573, 1, 0, %p312;
	add.s32 	%r1574, %r1573, %r1548;
	st.local.u32 	[%r38+8], %r1572;
	ld.const.u32 	%r1552, [__GPU_i2opi_f+12];
	mul.lo.s32 	%r1575, %r1552, %r1559;
	// inline asm
	mul.hi.u32 	%r1551, %r1552, %r1559;
	// inline asm
	mad.lo.s32 	%r1576, %r1552, %r1559, %r1574;
	setp.lt.u32 	%p313, %r1576, %r1575;
	selp.u32 	%r1577, 1, 0, %p313;
	add.s32 	%r1578, %r1577, %r1551;
	st.local.u32 	[%r38+12], %r1576;
	ld.const.u32 	%r1555, [__GPU_i2opi_f+16];
	mul.lo.s32 	%r1579, %r1555, %r1559;
	// inline asm
	mul.hi.u32 	%r1554, %r1555, %r1559;
	// inline asm
	mad.lo.s32 	%r1580, %r1555, %r1559, %r1578;
	setp.lt.u32 	%p314, %r1580, %r1579;
	selp.u32 	%r1581, 1, 0, %p314;
	add.s32 	%r1582, %r1581, %r1554;
	st.local.u32 	[%r38+16], %r1580;
	ld.const.u32 	%r1558, [__GPU_i2opi_f+20];
	mul.lo.s32 	%r1583, %r1558, %r1559;
	// inline asm
	mul.hi.u32 	%r1557, %r1558, %r1559;
	// inline asm
	mad.lo.s32 	%r1584, %r1558, %r1559, %r1582;
	setp.lt.u32 	%p315, %r1584, %r1583;
	selp.u32 	%r1585, 1, 0, %p315;
	add.s32 	%r1586, %r1585, %r1557;
	st.local.u32 	[%r38+20], %r1584;
	st.local.u32 	[%r38+24], %r1586;
	and.b32  	%r481, %r480, 31;
	shl.b32 	%r1588, %r1565, 2;
	add.s32 	%r1589, %r1588, %r38;
	add.s32 	%r482, %r1589, -16;
	ld.local.u32 	%r1834, [%r1589+8];
	ld.local.u32 	%r1835, [%r1589+4];
	setp.eq.s32 	%p316, %r481, 0;
	@%p316 bra 	BB13_340;

	shl.b32 	%r1590, %r1834, %r481;
	neg.s32 	%r1591, %r480;
	and.b32  	%r1592, %r1591, 31;
	shr.u32 	%r1593, %r1835, %r1592;
	or.b32  	%r1834, %r1593, %r1590;
	ld.local.u32 	%r1594, [%r482+16];
	shr.u32 	%r1595, %r1594, %r1592;
	shl.b32 	%r1596, %r1835, %r481;
	or.b32  	%r1835, %r1595, %r1596;

BB13_340:
	shr.u32 	%r1597, %r1835, 30;
	shl.b32 	%r1598, %r1834, 2;
	or.b32  	%r1840, %r1597, %r1598;
	shl.b32 	%r490, %r1835, 2;
	setp.ne.s32 	%p317, %r490, 0;
	selp.u32 	%r1599, 1, 0, %p317;
	add.s32 	%r1600, %r1599, %r1840;
	setp.gt.u32 	%p318, %r1600, -2147483648;
	selp.u32 	%r1601, 1, 0, %p318;
	shr.u32 	%r1602, %r1834, 30;
	add.s32 	%r1603, %r1601, %r1602;
	neg.s32 	%r1604, %r1603;
	setp.lt.s32 	%p319, %r478, 0;
	selp.b32 	%r1844, %r1604, %r1603, %p319;
	@%p318 bra 	BB13_342;

	mov.u32 	%r1839, %r490;
	bra.uni 	BB13_343;

BB13_342:
	not.b32 	%r1605, %r1840;
	neg.s32 	%r492, %r490;
	setp.eq.s32 	%p320, %r490, 0;
	selp.u32 	%r1606, 1, 0, %p320;
	add.s32 	%r1840, %r1606, %r1605;
	xor.b32  	%r1836, %r1836, -2147483648;
	mov.u32 	%r1839, %r492;

BB13_343:
	mov.u32 	%r1838, %r1839;
	setp.gt.s32 	%p321, %r1840, 0;
	@%p321 bra 	BB13_345;

	mov.u32 	%r1843, 0;
	bra.uni 	BB13_347;

BB13_345:
	mov.u32 	%r1843, 0;

BB13_346:
	shr.u32 	%r1609, %r1838, 31;
	shl.b32 	%r1610, %r1840, 1;
	or.b32  	%r1840, %r1609, %r1610;
	shl.b32 	%r1838, %r1838, 1;
	add.s32 	%r1843, %r1843, -1;
	setp.gt.s32 	%p322, %r1840, 0;
	@%p322 bra 	BB13_346;

BB13_347:
	mul.lo.s32 	%r1842, %r1840, -921707870;
	mov.u32 	%r1613, -921707870;
	// inline asm
	mul.hi.u32 	%r1611, %r1840, %r1613;
	// inline asm
	setp.gt.s32 	%p323, %r1611, 0;
	mov.u32 	%r1841, %r1611;
	@%p323 bra 	BB13_348;
	bra.uni 	BB13_349;

BB13_348:
	shl.b32 	%r1614, %r1611, 1;
	shr.u32 	%r1615, %r1842, 31;
	or.b32  	%r1841, %r1614, %r1615;
	mul.lo.s32 	%r1842, %r1840, -1843415740;
	add.s32 	%r1843, %r1843, -1;

BB13_349:
	setp.ne.s32 	%p324, %r1842, 0;
	selp.u32 	%r1616, 1, 0, %p324;
	add.s32 	%r1617, %r1616, %r1841;
	shr.u32 	%r1618, %r1617, 8;
	shr.u32 	%r1619, %r1617, 7;
	and.b32  	%r1620, %r1619, 1;
	shl.b32 	%r1621, %r1843, 23;
	add.s32 	%r1622, %r1621, %r1618;
	add.s32 	%r1623, %r1622, %r1620;
	add.s32 	%r1624, %r1623, 1056964608;
	or.b32  	%r1625, %r1624, %r1836;
	mov.b32 	 %f1082, %r1625;

BB13_350:
	add.s32 	%r515, %r1844, 1;
	and.b32  	%r1626, %r515, 1;
	setp.eq.s32 	%p325, %r1626, 0;
	mul.rn.f32 	%f192, %f1082, %f1082;
	@%p325 bra 	BB13_352;

	mov.f32 	%f800, 0f37CCF5CE;
	mul.rn.f32 	%f801, %f800, %f192;
	add.f32 	%f802, %f801, 0fBAB6061A;
	mul.rn.f32 	%f803, %f802, %f192;
	add.f32 	%f804, %f803, 0f3D2AAAA5;
	mul.rn.f32 	%f805, %f804, %f192;
	add.f32 	%f806, %f805, 0fBF000000;
	mul.rn.f32 	%f807, %f806, %f192;
	add.f32 	%f1083, %f807, 0f3F800000;
	bra.uni 	BB13_353;

BB13_352:
	mov.f32 	%f808, 0fB94CA1F9;
	mul.rn.f32 	%f809, %f808, %f192;
	add.f32 	%f810, %f809, 0f3C08839E;
	mul.rn.f32 	%f811, %f810, %f192;
	add.f32 	%f812, %f811, 0fBE2AAAA3;
	mul.rn.f32 	%f813, %f812, %f192;
	mul.rn.f32 	%f814, %f813, %f1082;
	add.f32 	%f1083, %f814, %f1082;

BB13_353:
	and.b32  	%r1627, %r515, 2;
	setp.eq.s32 	%p326, %r1627, 0;
	neg.f32 	%f815, %f1083;
	selp.f32 	%f196, %f1083, %f815, %p326;
	mov.f32 	%f1095, %f196;
	bra.uni 	BB13_355;

BB13_354:
	mov.f32 	%f1095, %f14;

BB13_355:
	mov.f32 	%f197, %f1095;
	mad.f32 	%f1109, %f197, 0f3F000000, 0f3F000000;
	bra.uni 	BB13_369;

BB13_356:
	setp.lt.f32 	%p327, %f567, 0f3F800000;
	mov.f32 	%f816, 0f3F800000;
	sub.f32 	%f817, %f816, %f567;
	selp.f32 	%f1109, %f817, 0f00000000, %p327;
	bra.uni 	BB13_369;

BB13_357:
	ld.param.u32 	%r1689, [ResizeVerticalFilter_param_10];
	ld.global.f32 	%f824, [%r1689];
	ld.global.f32 	%f825, [%r1689+8];
	ld.global.f32 	%f826, [%r1689+4];
	mad.f32 	%f827, %f567, %f825, %f826;
	mul.f32 	%f828, %f567, %f827;
	mad.f32 	%f1109, %f567, %f828, %f824;
	bra.uni 	BB13_369;

BB13_358:
	setp.neu.f32 	%p330, %f567, 0f00000000;
	@%p330 bra 	BB13_360;

BB13_359:
	mov.f32 	%f1109, 0f3F800000;
	bra.uni 	BB13_369;

BB13_360:
	mul.f32 	%f202, %f567, 0f40490FDC;
	setp.eq.f32 	%p331, %f567, %f12;
	@%p331 bra 	BB13_366;

	setp.eq.f32 	%p332, %f567, %f13;
	setp.eq.f32 	%p333, %f567, 0f00000000;
	or.pred  	%p334, %p332, %p333;
	@%p334 bra 	BB13_366;

	mov.f32 	%f834, 0f40000000;
	mul.rn.f32 	%f831, %f834, %f567;
	// inline asm
	cvt.rni.f32.f32 	%f830, %f831;
	// inline asm
	cvt.rzi.s32.f32 	%r1628, %f830;
	neg.f32 	%f835, %f830;
	mul.rn.f32 	%f837, %f835, %f237;
	add.f32 	%f838, %f837, %f567;
	mov.f32 	%f839, 0f40490FDB;
	mul.rn.f32 	%f840, %f838, %f839;
	// inline asm
	abs.f32 	%f832, %f567;
	// inline asm
	setp.gt.f32 	%p335, %f832, 0f4B800000;
	selp.f32 	%f203, 0f00000000, %f840, %p335;
	selp.b32 	%r516, 0, %r1628, %p335;
	and.b32  	%r1629, %r516, 1;
	setp.eq.s32 	%p336, %r1629, 0;
	mul.rn.f32 	%f204, %f203, %f203;
	@%p336 bra 	BB13_364;

	mov.f32 	%f841, 0f37CCF5CE;
	mul.rn.f32 	%f842, %f841, %f204;
	add.f32 	%f843, %f842, 0fBAB6061A;
	mul.rn.f32 	%f844, %f843, %f204;
	add.f32 	%f845, %f844, 0f3D2AAAA5;
	mul.rn.f32 	%f846, %f845, %f204;
	add.f32 	%f847, %f846, 0fBF000000;
	mul.rn.f32 	%f848, %f847, %f204;
	add.f32 	%f1107, %f848, 0f3F800000;
	bra.uni 	BB13_365;

BB13_364:
	mov.f32 	%f849, 0fB94CA1F9;
	mul.rn.f32 	%f850, %f849, %f204;
	add.f32 	%f851, %f850, 0f3C08839E;
	mul.rn.f32 	%f852, %f851, %f204;
	add.f32 	%f853, %f852, 0fBE2AAAA3;
	mul.rn.f32 	%f854, %f853, %f204;
	mul.rn.f32 	%f855, %f854, %f203;
	add.f32 	%f1107, %f855, %f203;

BB13_365:
	and.b32  	%r1630, %r516, 2;
	setp.eq.s32 	%p337, %r1630, 0;
	neg.f32 	%f856, %f1107;
	selp.f32 	%f1108, %f1107, %f856, %p337;
	bra.uni 	BB13_367;

BB13_366:
	mov.f32 	%f857, 0f00000000;
	mul.rn.f32 	%f1108, %f567, %f857;

BB13_367:
	div.full.f32 	%f1109, %f1108, %f202;
	bra.uni 	BB13_369;

BB13_368:
	mov.f32 	%f1109, 0f00000000;

BB13_369:
	mul.f32 	%f859, %f1077, %f1109;
	mad.f32 	%f1124, %f859, %f1015, %f1124;
	mad.f32 	%f1125, %f859, %f1016, %f1125;
	mad.f32 	%f1126, %f859, %f1017, %f1126;
	mad.f32 	%f1127, %f859, %f1018, %f1127;
	mad.f32 	%f1110, %f1077, %f1109, %f1110;
	add.s32 	%r1778, %r1778, 1;
	add.s32 	%r1777, %r1777, 1;
	setp.lt.u32 	%p338, %r1777, %r573;
	@%p338 bra 	BB13_192;

	mov.f32 	%f1111, 0f00000000;
	bra.uni 	BB13_372;

BB13_371:
	mov.f32 	%f1111, 0f00000000;
	mov.f32 	%f1124, %f1111;
	mov.f32 	%f1125, %f1111;
	mov.f32 	%f1126, %f1111;
	mov.f32 	%f1127, %f1111;
	mov.f32 	%f1110, %f1111;

BB13_372:
	shl.b32 	%r1631, %r562, 4;
	ld.param.u32 	%r1704, [ResizeVerticalFilter_param_19];
	add.s32 	%r519, %r1704, %r1631;
	shl.b32 	%r1632, %r562, 2;
	ld.param.u32 	%r1706, [ResizeVerticalFilter_param_20];
	add.s32 	%r520, %r1706, %r1632;
	ld.param.u32 	%r1708, [ResizeVerticalFilter_param_21];
	add.s32 	%r521, %r1708, %r1632;
	setp.lt.u32 	%p4, %r562, %r28;
	setp.ge.u32 	%p339, %r562, %r28;
	@%p339 bra 	BB13_375;

	mov.f32 	%f866, 0f00000000;
	st.shared.v4.f32 	[%r519], {%f866, %f866, %f866, %f866};
	mov.u32 	%r1633, 0;
	st.shared.u32 	[%r520], %r1633;
	ld.param.u32 	%r1648, [ResizeVerticalFilter_param_3];
	setp.eq.s32 	%p340, %r1648, 0;
	@%p340 bra 	BB13_375;

	st.shared.u32 	[%r521], %r1633;

BB13_375:
	bar.sync 	0;
	setp.eq.s32 	%p341, %r30, 0;
	@%p341 bra 	BB13_382;

	shl.b32 	%r1636, %r31, 4;
	ld.param.u32 	%r1703, [ResizeVerticalFilter_param_19];
	add.s32 	%r522, %r1703, %r1636;
	shl.b32 	%r1637, %r31, 2;
	ld.param.u32 	%r1705, [ResizeVerticalFilter_param_20];
	add.s32 	%r523, %r1705, %r1637;
	ld.param.u32 	%r1707, [ResizeVerticalFilter_param_21];
	add.s32 	%r524, %r1707, %r1637;
	mov.u32 	%r1845, 0;

BB13_377:
	@%p2 bra 	BB13_381;

	rem.u32 	%r1638, %r562, %r30;
	setp.ne.s32 	%p342, %r1845, %r1638;
	@%p342 bra 	BB13_381;

	ld.shared.v4.f32 	{%f975, %f976, %f977, %f978}, [%r522];
	add.f32 	%f979, %f975, %f1124;
	add.f32 	%f980, %f976, %f1125;
	add.f32 	%f981, %f977, %f1126;
	add.f32 	%f982, %f978, %f1127;
	st.shared.v4.f32 	[%r522], {%f979, %f980, %f981, %f982};
	ld.shared.f32 	%f867, [%r523];
	add.f32 	%f868, %f867, %f1110;
	st.shared.f32 	[%r523], %f868;
	ld.param.u32 	%r1647, [ResizeVerticalFilter_param_3];
	setp.eq.s32 	%p343, %r1647, 0;
	@%p343 bra 	BB13_381;

	ld.shared.f32 	%f869, [%r524];
	add.f32 	%f870, %f869, %f1111;
	st.shared.f32 	[%r524], %f870;

BB13_381:
	bar.sync 	0;
	add.s32 	%r1845, %r1845, 1;
	setp.lt.u32 	%p344, %r1845, %r30;
	@%p344 bra 	BB13_377;

BB13_382:
	@!%p4 bra 	BB13_399;

	ld.shared.f32 	%f216, [%r520];
	setp.neu.f32 	%p345, %f216, 0f00000000;
	setp.neu.f32 	%p346, %f216, 0f3F800000;
	and.pred  	%p5, %p345, %p346;
	add.s32 	%r1639, %r562, %r27;
	ld.param.u32 	%r1651, [ResizeVerticalFilter_param_6];
	mad.lo.s32 	%r1640, %r1639, %r1651, %r19;
	shl.b32 	%r1641, %r1640, 4;
	ld.param.u32 	%r1650, [ResizeVerticalFilter_param_5];
	add.s32 	%r527, %r1650, %r1641;
	ld.param.u32 	%r1646, [ResizeVerticalFilter_param_3];
	setp.eq.s32 	%p347, %r1646, 0;
	@%p347 bra 	BB13_393;

	ld.shared.f32 	%f1113, [%r521];
	ld.shared.v4.f32 	{%f1120, %f1121, %f1122, %f1123}, [%r519];
	@%p5 bra 	BB13_385;
	bra.uni 	BB13_389;

BB13_385:
	setp.lt.f32 	%p348, %f216, 0f00000000;
	selp.f32 	%f218, 0fBF800000, 0f3F800000, %p348;
	mul.f32 	%f871, %f218, %f216;
	setp.ltu.f32 	%p349, %f871, 0f00000000;
	@%p349 bra 	BB13_387;

	rcp.approx.f32 	%f1112, %f216;
	bra.uni 	BB13_388;

BB13_387:
	mul.f32 	%f1112, %f218, 0f7F800000;

BB13_388:
	mul.f32 	%f1120, %f1120, %f1112;
	mul.f32 	%f1121, %f1121, %f1112;
	mul.f32 	%f1122, %f1122, %f1112;
	mul.f32 	%f1123, %f1123, %f1112;
	mul.f32 	%f1113, %f1113, %f1112;

BB13_389:
	setp.lt.f32 	%p350, %f1113, 0f00000000;
	selp.f32 	%f224, 0fBF800000, 0f3F800000, %p350;
	mul.f32 	%f875, %f224, %f1113;
	setp.ltu.f32 	%p351, %f875, 0f00000000;
	@%p351 bra 	BB13_391;

	rcp.approx.f32 	%f1114, %f1113;
	bra.uni 	BB13_392;

BB13_391:
	mul.f32 	%f1114, %f224, 0f7F800000;

BB13_392:
	mul.f32 	%f877, %f1114, %f1120;
	mov.f32 	%f878, 0f00000000;
	max.f32 	%f879, %f877, %f878;
	mov.f32 	%f880, 0f477FFF00;
	min.f32 	%f881, %f879, %f880;
	add.f32 	%f882, %f881, 0f3F000000;
	mul.f32 	%f884, %f1114, %f1121;
	max.f32 	%f885, %f884, %f878;
	min.f32 	%f886, %f885, %f880;
	add.f32 	%f887, %f886, 0f3F000000;
	mul.f32 	%f889, %f1114, %f1122;
	max.f32 	%f890, %f889, %f878;
	min.f32 	%f891, %f890, %f880;
	add.f32 	%f892, %f891, 0f3F000000;
	max.f32 	%f894, %f1123, %f878;
	min.f32 	%f895, %f894, %f880;
	add.f32 	%f896, %f895, 0f3F000000;
	st.global.v4.f32 	[%r527], {%f882, %f887, %f892, %f896};
	bra.uni 	BB13_399;

BB13_393:
	ld.shared.v4.f32 	{%f1116, %f1117, %f1118, %f1119}, [%r519];
	@%p5 bra 	BB13_394;
	bra.uni 	BB13_398;

BB13_394:
	setp.lt.f32 	%p352, %f216, 0f00000000;
	selp.f32 	%f228, 0fBF800000, 0f3F800000, %p352;
	mul.f32 	%f897, %f228, %f216;
	setp.ltu.f32 	%p353, %f897, 0f00000000;
	@%p353 bra 	BB13_396;

	rcp.approx.f32 	%f1115, %f216;
	bra.uni 	BB13_397;

BB13_396:
	mul.f32 	%f1115, %f228, 0f7F800000;

BB13_397:
	mul.f32 	%f1116, %f1116, %f1115;
	mul.f32 	%f1117, %f1117, %f1115;
	mul.f32 	%f1118, %f1118, %f1115;
	mul.f32 	%f1119, %f1119, %f1115;

BB13_398:
	mov.f32 	%f902, 0f00000000;
	max.f32 	%f903, %f1116, %f902;
	mov.f32 	%f904, 0f477FFF00;
	min.f32 	%f905, %f903, %f904;
	add.f32 	%f906, %f905, 0f3F000000;
	max.f32 	%f908, %f1117, %f902;
	min.f32 	%f909, %f908, %f904;
	add.f32 	%f910, %f909, 0f3F000000;
	max.f32 	%f912, %f1118, %f902;
	min.f32 	%f913, %f912, %f904;
	add.f32 	%f914, %f913, 0f3F000000;
	max.f32 	%f916, %f1119, %f902;
	min.f32 	%f917, %f916, %f904;
	add.f32 	%f918, %f917, 0f3F000000;
	st.global.v4.f32 	[%r527], {%f906, %f910, %f914, %f918};

BB13_399:
	add.s32 	%r1710, %r1710, 1;
	setp.lt.u32 	%p354, %r1710, %r25;
	@%p354 bra 	BB13_7;

BB13_400:
	ret;
}

.entry ResizeVerticalFilterSinc(
	.param .u32 .ptr .global .align 16 ResizeVerticalFilterSinc_param_0,
	.param .u32 ResizeVerticalFilterSinc_param_1,
	.param .u32 ResizeVerticalFilterSinc_param_2,
	.param .u32 ResizeVerticalFilterSinc_param_3,
	.param .f32 ResizeVerticalFilterSinc_param_4,
	.param .u32 .ptr .global .align 16 ResizeVerticalFilterSinc_param_5,
	.param .u32 ResizeVerticalFilterSinc_param_6,
	.param .u32 ResizeVerticalFilterSinc_param_7,
	.param .u32 ResizeVerticalFilterSinc_param_8,
	.param .u32 ResizeVerticalFilterSinc_param_9,
	.param .u32 .ptr .global .align 4 ResizeVerticalFilterSinc_param_10,
	.param .f32 ResizeVerticalFilterSinc_param_11,
	.param .f32 ResizeVerticalFilterSinc_param_12,
	.param .f32 ResizeVerticalFilterSinc_param_13,
	.param .f32 ResizeVerticalFilterSinc_param_14,
	.param .u32 .ptr .shared .align 16 ResizeVerticalFilterSinc_param_15,
	.param .u32 ResizeVerticalFilterSinc_param_16,
	.param .u32 ResizeVerticalFilterSinc_param_17,
	.param .u32 ResizeVerticalFilterSinc_param_18,
	.param .u32 .ptr .shared .align 16 ResizeVerticalFilterSinc_param_19,
	.param .u32 .ptr .shared .align 4 ResizeVerticalFilterSinc_param_20,
	.param .u32 .ptr .shared .align 4 ResizeVerticalFilterSinc_param_21
)
.reqntid 1, 256, 1
{
	.reg .f32 	%f<480>;
	.reg .pred 	%p<66>;
	.reg .s32 	%r<189>;


	ld.param.f32 	%f1, [ResizeVerticalFilterSinc_param_4];
	ld.param.u32 	%r73, [ResizeVerticalFilterSinc_param_7];
	ld.param.f32 	%f86, [ResizeVerticalFilterSinc_param_12];
	ld.param.u32 	%r9, [ResizeVerticalFilterSinc_param_17];
	// inline asm
	mov.u32 	%r69, %envreg1;
	// inline asm
	// inline asm
	mov.u32 	%r70, %ctaid.y;
	// inline asm
	add.s32 	%r74, %r70, %r69;
	mul.lo.s32 	%r16, %r74, %r9;
	mad.lo.s32 	%r72, %r74, %r9, %r9;
	// inline asm
	min.u32 	%r71, %r72, %r73;
	// inline asm
	rcp.approx.f32 	%f87, %f1;
	mov.f32 	%f88, 0f3F800000;
	add.f32 	%f89, %f87, 0f00000000;
	max.f32 	%f5, %f89, %f88;
	mul.f32 	%f90, %f5, %f86;
	mov.f32 	%f91, 0f3F000000;
	max.f32 	%f6, %f90, %f91;
	setp.lt.f32 	%p7, %f5, 0f00000000;
	selp.f32 	%f7, 0fBF800000, 0f3F800000, %p7;
	mul.f32 	%f92, %f7, %f5;
	setp.ltu.f32 	%p8, %f92, 0f00000000;
	@%p8 bra 	BB14_2;

	rcp.approx.f32 	%f449, %f5;
	bra.uni 	BB14_3;

BB14_2:
	mul.f32 	%f449, %f7, 0f7F800000;

BB14_3:
	cvt.rn.f32.u32 	%f93, %r16;
	add.f32 	%f94, %f93, 0f3F000000;
	ld.param.f32 	%f442, [ResizeVerticalFilterSinc_param_4];
	div.full.f32 	%f95, %f94, %f442;
	add.f32 	%f96, %f95, 0f00000000;
	sub.f32 	%f97, %f96, %f6;
	add.f32 	%f98, %f97, 0f3F000000;
	cvt.rzi.s32.f32 	%r76, %f98;
	mov.u32 	%r77, 0;
	// inline asm
	max.s32 	%r75, %r76, %r77;
	// inline asm
	ld.param.u32 	%r171, [ResizeVerticalFilterSinc_param_16];
	add.s32 	%r79, %r75, %r171;
	ld.param.u32 	%r160, [ResizeVerticalFilterSinc_param_2];
	// inline asm
	min.s32 	%r78, %r79, %r160;
	// inline asm
	// inline asm
	mov.u32 	%r81, %envreg3;
	// inline asm
	// inline asm
	mov.u32 	%r82, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r83, %ctaid.x;
	// inline asm
	// inline asm
	mov.u32 	%r84, %tid.x;
	// inline asm
	add.s32 	%r87, %r84, %r81;
	mad.lo.s32 	%r19, %r83, %r82, %r87;
	sub.s32 	%r20, %r78, %r75;
	// inline asm
	mov.u32 	%r85, %ntid.x;
	// inline asm
	// inline asm
	mov.u32 	%r86, %tid.x;
	// inline asm
	setp.ge.u32 	%p9, %r86, %r20;
	mov.u32 	%r182, %r86;
	@%p9 bra 	BB14_5;

BB14_4:
	add.s32 	%r88, %r182, %r75;
	ld.param.u32 	%r159, [ResizeVerticalFilterSinc_param_1];
	mad.lo.s32 	%r89, %r88, %r159, %r19;
	shl.b32 	%r90, %r89, 4;
	ld.param.u32 	%r158, [ResizeVerticalFilterSinc_param_0];
	add.s32 	%r91, %r158, %r90;
	shl.b32 	%r92, %r182, 4;
	ld.param.u32 	%r170, [ResizeVerticalFilterSinc_param_15];
	add.s32 	%r93, %r170, %r92;
	ld.global.v4.f32 	{%f437, %f438, %f439, %f440}, [%r91];
	st.shared.v4.f32 	[%r93], {%f437, %f438, %f439, %f440};
	add.s32 	%r182, %r182, %r85;
	setp.lt.u32 	%p10, %r182, %r20;
	@%p10 bra 	BB14_4;

BB14_5:
	membar.gl;
	bar.sync 	0;
	ld.param.u32 	%r173, [ResizeVerticalFilterSinc_param_18];
	add.s32 	%r94, %r173, %r71;
	add.s32 	%r95, %r94, -1;
	sub.s32 	%r96, %r95, %r16;
	div.u32 	%r25, %r96, %r173;
	setp.eq.s32 	%p11, %r25, 0;
	@%p11 bra 	BB14_88;

	ld.param.u32 	%r161, [ResizeVerticalFilterSinc_param_2];
	cvt.rn.f32.u32 	%f11, %r161;
	mov.f32 	%f12, 0fFF800000;
	neg.s32 	%r26, %r75;
	mov.u32 	%r184, 0;
	ld.param.u32 	%r172, [ResizeVerticalFilterSinc_param_17];
	mul.lo.s32 	%r99, %r172, %r74;
	neg.s32 	%r183, %r99;

BB14_7:
	ld.param.u32 	%r175, [ResizeVerticalFilterSinc_param_18];
	mad.lo.s32 	%r30, %r184, %r175, %r16;
	add.s32 	%r101, %r30, %r175;
	// inline asm
	min.u32 	%r100, %r101, %r71;
	// inline asm
	sub.s32 	%r32, %r100, %r30;
	// inline asm
	mov.u32 	%r103, %tid.y;
	// inline asm
	// inline asm
	mov.u32 	%r104, %ntid.y;
	// inline asm
	div.u32 	%r35, %r104, %r32;
	// inline asm
	mov.u32 	%r105, %ntid.y;
	// inline asm
	div.u32 	%r106, %r105, %r32;
	div.u32 	%r107, %r103, %r106;
	setp.lt.u32 	%p12, %r107, %r32;
	selp.b32 	%r36, %r107, -1, %p12;
	setp.eq.s32 	%p1, %r36, -1;
	@%p1 bra 	BB14_59;

	add.s32 	%r108, %r36, %r30;
	cvt.rn.f32.s32 	%f99, %r108;
	add.f32 	%f100, %f99, 0f3F000000;
	ld.param.f32 	%f441, [ResizeVerticalFilterSinc_param_4];
	div.full.f32 	%f101, %f100, %f441;
	add.f32 	%f13, %f101, 0f00000000;
	mov.f32 	%f462, 0f00000000;
	sub.f32 	%f103, %f13, %f6;
	add.f32 	%f104, %f103, 0f3F000000;
	max.f32 	%f105, %f104, %f462;
	cvt.rzi.u32.f32 	%r37, %f105;
	add.f32 	%f106, %f13, %f6;
	add.f32 	%f107, %f106, 0f3F000000;
	min.f32 	%f108, %f107, %f11;
	cvt.rzi.u32.f32 	%r38, %f108;
	sub.s32 	%r39, %r38, %r37;
	div.u32 	%r109, %r39, %r35;
	mul.lo.s32 	%r110, %r109, %r35;
	setp.ne.s32 	%p2, %r110, %r39;
	selp.u32 	%r111, 1, 0, %p2;
	add.s32 	%r40, %r111, %r109;
	rem.u32 	%r41, %r103, %r35;
	mul.lo.s32 	%r187, %r40, %r41;
	setp.ge.u32 	%p13, %r187, %r39;
	@%p13 bra 	BB14_59;

	add.s32 	%r113, %r187, %r40;
	// inline asm
	min.u32 	%r112, %r113, %r39;
	// inline asm
	setp.lt.u32 	%p3, %r187, %r112;
	ld.param.u32 	%r165, [ResizeVerticalFilterSinc_param_3];
	setp.eq.s32 	%p14, %r165, 0;
	@%p14 bra 	BB14_34;

	@!%p3 bra 	BB14_59;

	add.s32 	%r115, %r26, %r37;
	add.s32 	%r116, %r100, %r183;
	div.u32 	%r117, %r104, %r116;
	div.u32 	%r119, %r39, %r117;
	add.s32 	%r121, %r119, %r111;
	mad.lo.s32 	%r122, %r41, %r121, %r115;
	shl.b32 	%r123, %r122, 4;
	ld.param.u32 	%r169, [ResizeVerticalFilterSinc_param_15];
	add.s32 	%r185, %r169, %r123;
	mov.f32 	%f476, %f462;
	mov.f32 	%f477, %f462;
	mov.f32 	%f478, %f462;
	mov.f32 	%f479, %f462;
	mov.f32 	%f463, %f462;

BB14_12:
	ld.shared.v4.f32 	{%f425, %f426, %f427, %f428}, [%r185];
	add.s32 	%r124, %r37, %r187;
	cvt.rn.f32.u32 	%f113, %r124;
	sub.f32 	%f114, %f113, %f13;
	add.f32 	%f115, %f114, 0f3F000000;
	mul.f32 	%f116, %f449, %f115;
	ld.param.f32 	%f448, [ResizeVerticalFilterSinc_param_14];
	div.full.f32 	%f112, %f116, %f448;
	// inline asm
	abs.f32 	%f111, %f112;
	// inline asm
	ld.param.f32 	%f446, [ResizeVerticalFilterSinc_param_13];
	setp.lt.f32 	%p15, %f446, 0f00000000;
	@%p15 bra 	BB14_22;

	ld.param.f32 	%f443, [ResizeVerticalFilterSinc_param_11];
	mul.f32 	%f17, %f111, %f443;
	setp.eq.f32 	%p16, %f17, 0f00000000;
	@%p16 bra 	BB14_22;

	mul.f32 	%f18, %f17, 0f40490FDC;
	setp.eq.f32 	%p17, %f17, 0f7F800000;
	@%p17 bra 	BB14_20;

	setp.eq.f32 	%p18, %f17, %f12;
	or.pred  	%p20, %p18, %p16;
	@%p20 bra 	BB14_20;

	mov.f32 	%f121, 0f40000000;
	mul.rn.f32 	%f118, %f121, %f17;
	// inline asm
	cvt.rni.f32.f32 	%f117, %f118;
	// inline asm
	cvt.rzi.s32.f32 	%r125, %f117;
	neg.f32 	%f122, %f117;
	mul.rn.f32 	%f124, %f122, %f91;
	add.f32 	%f125, %f124, %f17;
	mov.f32 	%f126, 0f40490FDB;
	mul.rn.f32 	%f127, %f125, %f126;
	// inline asm
	abs.f32 	%f119, %f17;
	// inline asm
	setp.gt.f32 	%p21, %f119, 0f4B800000;
	selp.f32 	%f19, 0f00000000, %f127, %p21;
	selp.b32 	%r47, 0, %r125, %p21;
	and.b32  	%r126, %r47, 1;
	setp.eq.s32 	%p22, %r126, 0;
	mul.rn.f32 	%f20, %f19, %f19;
	@%p22 bra 	BB14_18;

	mov.f32 	%f128, 0f37CCF5CE;
	mul.rn.f32 	%f129, %f128, %f20;
	add.f32 	%f130, %f129, 0fBAB6061A;
	mul.rn.f32 	%f131, %f130, %f20;
	add.f32 	%f132, %f131, 0f3D2AAAA5;
	mul.rn.f32 	%f133, %f132, %f20;
	add.f32 	%f134, %f133, 0fBF000000;
	mul.rn.f32 	%f135, %f134, %f20;
	add.f32 	%f450, %f135, 0f3F800000;
	bra.uni 	BB14_19;

BB14_18:
	mov.f32 	%f136, 0fB94CA1F9;
	mul.rn.f32 	%f137, %f136, %f20;
	add.f32 	%f138, %f137, 0f3C08839E;
	mul.rn.f32 	%f139, %f138, %f20;
	add.f32 	%f140, %f139, 0fBE2AAAA3;
	mul.rn.f32 	%f141, %f140, %f20;
	mul.rn.f32 	%f142, %f141, %f19;
	add.f32 	%f450, %f142, %f19;

BB14_19:
	and.b32  	%r127, %r47, 2;
	setp.eq.s32 	%p23, %r127, 0;
	neg.f32 	%f143, %f450;
	selp.f32 	%f451, %f450, %f143, %p23;
	bra.uni 	BB14_21;

BB14_20:
	mov.f32 	%f144, 0f00000000;
	mul.rn.f32 	%f451, %f17, %f144;

BB14_21:
	div.full.f32 	%f452, %f451, %f18;
	bra.uni 	BB14_23;

BB14_22:
	mov.f32 	%f452, 0f3F800000;

BB14_23:
	setp.neu.f32 	%p24, %f111, 0f00000000;
	@%p24 bra 	BB14_25;

	mov.f32 	%f455, %f88;
	bra.uni 	BB14_33;

BB14_25:
	mul.f32 	%f29, %f111, 0f40490FDC;
	setp.eq.f32 	%p25, %f111, 0f7F800000;
	@%p25 bra 	BB14_31;

	setp.eq.f32 	%p26, %f111, %f12;
	setp.eq.f32 	%p27, %f111, 0f00000000;
	or.pred  	%p28, %p26, %p27;
	@%p28 bra 	BB14_31;

	mov.f32 	%f151, 0f40000000;
	mul.rn.f32 	%f148, %f151, %f111;
	// inline asm
	cvt.rni.f32.f32 	%f147, %f148;
	// inline asm
	cvt.rzi.s32.f32 	%r128, %f147;
	neg.f32 	%f152, %f147;
	mul.rn.f32 	%f154, %f152, %f91;
	add.f32 	%f155, %f154, %f111;
	mov.f32 	%f156, 0f40490FDB;
	mul.rn.f32 	%f157, %f155, %f156;
	// inline asm
	abs.f32 	%f149, %f111;
	// inline asm
	setp.gt.f32 	%p29, %f149, 0f4B800000;
	selp.f32 	%f30, 0f00000000, %f157, %p29;
	selp.b32 	%r48, 0, %r128, %p29;
	and.b32  	%r129, %r48, 1;
	setp.eq.s32 	%p30, %r129, 0;
	mul.rn.f32 	%f31, %f30, %f30;
	@%p30 bra 	BB14_29;

	mov.f32 	%f158, 0f37CCF5CE;
	mul.rn.f32 	%f159, %f158, %f31;
	add.f32 	%f160, %f159, 0fBAB6061A;
	mul.rn.f32 	%f161, %f160, %f31;
	add.f32 	%f162, %f161, 0f3D2AAAA5;
	mul.rn.f32 	%f163, %f162, %f31;
	add.f32 	%f164, %f163, 0fBF000000;
	mul.rn.f32 	%f165, %f164, %f31;
	add.f32 	%f453, %f165, 0f3F800000;
	bra.uni 	BB14_30;

BB14_29:
	mov.f32 	%f166, 0fB94CA1F9;
	mul.rn.f32 	%f167, %f166, %f31;
	add.f32 	%f168, %f167, 0f3C08839E;
	mul.rn.f32 	%f169, %f168, %f31;
	add.f32 	%f170, %f169, 0fBE2AAAA3;
	mul.rn.f32 	%f171, %f170, %f31;
	mul.rn.f32 	%f172, %f171, %f30;
	add.f32 	%f453, %f172, %f30;

BB14_30:
	and.b32  	%r130, %r48, 2;
	setp.eq.s32 	%p31, %r130, 0;
	neg.f32 	%f173, %f453;
	selp.f32 	%f454, %f453, %f173, %p31;
	bra.uni 	BB14_32;

BB14_31:
	mov.f32 	%f174, 0f00000000;
	mul.rn.f32 	%f454, %f111, %f174;

BB14_32:
	div.full.f32 	%f38, %f454, %f29;
	mov.f32 	%f455, %f38;

BB14_33:
	mov.f32 	%f39, %f455;
	mul.f32 	%f175, %f452, %f39;
	mul.f32 	%f176, %f175, 0f377BA882;
	mov.f32 	%f178, 0f477FFF00;
	sub.f32 	%f179, %f178, %f428;
	mul.f32 	%f180, %f176, %f179;
	mad.f32 	%f183, %f180, %f425, %f476;
	mad.f32 	%f186, %f180, %f426, %f477;
	mad.f32 	%f189, %f180, %f427, %f478;
	mad.f32 	%f191, %f175, %f428, %f479;
	mov.f32 	%f476, %f183;
	mov.f32 	%f477, %f186;
	mov.f32 	%f478, %f189;
	mov.f32 	%f479, %f191;
	mad.f32 	%f462, %f452, %f39, %f462;
	mad.f32 	%f463, %f176, %f179, %f463;
	add.s32 	%r185, %r185, 16;
	add.s32 	%r187, %r187, 1;
	setp.lt.u32 	%p32, %r187, %r112;
	@%p32 bra 	BB14_12;
	bra.uni 	BB14_60;

BB14_34:
	@!%p3 bra 	BB14_59;

	add.s32 	%r131, %r26, %r37;
	add.s32 	%r132, %r100, %r183;
	div.u32 	%r133, %r104, %r132;
	div.u32 	%r135, %r39, %r133;
	add.s32 	%r137, %r135, %r111;
	mad.lo.s32 	%r138, %r41, %r137, %r131;
	shl.b32 	%r139, %r138, 4;
	ld.param.u32 	%r168, [ResizeVerticalFilterSinc_param_15];
	add.s32 	%r186, %r168, %r139;
	ld.param.f32 	%f445, [ResizeVerticalFilterSinc_param_13];
	setp.lt.f32 	%p4, %f445, 0f00000000;
	mov.f32 	%f462, 0f00000000;
	mov.f32 	%f476, %f462;
	mov.f32 	%f477, %f462;
	mov.f32 	%f478, %f462;
	mov.f32 	%f479, %f462;

BB14_36:
	ld.shared.v4.f32 	{%f413, %f414, %f415, %f416}, [%r186];
	add.s32 	%r140, %r37, %r187;
	cvt.rn.f32.u32 	%f195, %r140;
	sub.f32 	%f196, %f195, %f13;
	add.f32 	%f197, %f196, 0f3F000000;
	mul.f32 	%f198, %f449, %f197;
	ld.param.f32 	%f447, [ResizeVerticalFilterSinc_param_14];
	div.full.f32 	%f194, %f198, %f447;
	// inline asm
	abs.f32 	%f193, %f194;
	// inline asm
	@%p4 bra 	BB14_46;

	ld.param.f32 	%f444, [ResizeVerticalFilterSinc_param_11];
	mul.f32 	%f44, %f193, %f444;
	setp.eq.f32 	%p33, %f44, 0f00000000;
	@%p33 bra 	BB14_46;

	mul.f32 	%f45, %f44, 0f40490FDC;
	setp.eq.f32 	%p34, %f44, 0f7F800000;
	@%p34 bra 	BB14_44;

	setp.eq.f32 	%p35, %f44, %f12;
	or.pred  	%p37, %p35, %p33;
	@%p37 bra 	BB14_44;

	mov.f32 	%f203, 0f40000000;
	mul.rn.f32 	%f200, %f203, %f44;
	// inline asm
	cvt.rni.f32.f32 	%f199, %f200;
	// inline asm
	cvt.rzi.s32.f32 	%r141, %f199;
	neg.f32 	%f204, %f199;
	mul.rn.f32 	%f206, %f204, %f91;
	add.f32 	%f207, %f206, %f44;
	mov.f32 	%f208, 0f40490FDB;
	mul.rn.f32 	%f209, %f207, %f208;
	// inline asm
	abs.f32 	%f201, %f44;
	// inline asm
	setp.gt.f32 	%p38, %f201, 0f4B800000;
	selp.f32 	%f46, 0f00000000, %f209, %p38;
	selp.b32 	%r54, 0, %r141, %p38;
	and.b32  	%r142, %r54, 1;
	setp.eq.s32 	%p39, %r142, 0;
	mul.rn.f32 	%f47, %f46, %f46;
	@%p39 bra 	BB14_42;

	mov.f32 	%f210, 0f37CCF5CE;
	mul.rn.f32 	%f211, %f210, %f47;
	add.f32 	%f212, %f211, 0fBAB6061A;
	mul.rn.f32 	%f213, %f212, %f47;
	add.f32 	%f214, %f213, 0f3D2AAAA5;
	mul.rn.f32 	%f215, %f214, %f47;
	add.f32 	%f216, %f215, 0fBF000000;
	mul.rn.f32 	%f217, %f216, %f47;
	add.f32 	%f456, %f217, 0f3F800000;
	bra.uni 	BB14_43;

BB14_42:
	mov.f32 	%f218, 0fB94CA1F9;
	mul.rn.f32 	%f219, %f218, %f47;
	add.f32 	%f220, %f219, 0f3C08839E;
	mul.rn.f32 	%f221, %f220, %f47;
	add.f32 	%f222, %f221, 0fBE2AAAA3;
	mul.rn.f32 	%f223, %f222, %f47;
	mul.rn.f32 	%f224, %f223, %f46;
	add.f32 	%f456, %f224, %f46;

BB14_43:
	and.b32  	%r143, %r54, 2;
	setp.eq.s32 	%p40, %r143, 0;
	neg.f32 	%f225, %f456;
	selp.f32 	%f457, %f456, %f225, %p40;
	bra.uni 	BB14_45;

BB14_44:
	mov.f32 	%f226, 0f00000000;
	mul.rn.f32 	%f457, %f44, %f226;

BB14_45:
	div.full.f32 	%f458, %f457, %f45;
	bra.uni 	BB14_47;

BB14_46:
	mov.f32 	%f458, 0f3F800000;

BB14_47:
	setp.neu.f32 	%p41, %f193, 0f00000000;
	@%p41 bra 	BB14_49;

	mov.f32 	%f461, 0f3F800000;
	bra.uni 	BB14_57;

BB14_49:
	mul.f32 	%f56, %f193, 0f40490FDC;
	setp.eq.f32 	%p42, %f193, 0f7F800000;
	@%p42 bra 	BB14_55;

	setp.eq.f32 	%p43, %f193, %f12;
	setp.eq.f32 	%p44, %f193, 0f00000000;
	or.pred  	%p45, %p43, %p44;
	@%p45 bra 	BB14_55;

	mov.f32 	%f233, 0f40000000;
	mul.rn.f32 	%f230, %f233, %f193;
	// inline asm
	cvt.rni.f32.f32 	%f229, %f230;
	// inline asm
	cvt.rzi.s32.f32 	%r144, %f229;
	neg.f32 	%f234, %f229;
	mul.rn.f32 	%f236, %f234, %f91;
	add.f32 	%f237, %f236, %f193;
	mov.f32 	%f238, 0f40490FDB;
	mul.rn.f32 	%f239, %f237, %f238;
	// inline asm
	abs.f32 	%f231, %f193;
	// inline asm
	setp.gt.f32 	%p46, %f231, 0f4B800000;
	selp.f32 	%f57, 0f00000000, %f239, %p46;
	selp.b32 	%r55, 0, %r144, %p46;
	and.b32  	%r145, %r55, 1;
	setp.eq.s32 	%p47, %r145, 0;
	mul.rn.f32 	%f58, %f57, %f57;
	@%p47 bra 	BB14_53;

	mov.f32 	%f240, 0f37CCF5CE;
	mul.rn.f32 	%f241, %f240, %f58;
	add.f32 	%f242, %f241, 0fBAB6061A;
	mul.rn.f32 	%f243, %f242, %f58;
	add.f32 	%f244, %f243, 0f3D2AAAA5;
	mul.rn.f32 	%f245, %f244, %f58;
	add.f32 	%f246, %f245, 0fBF000000;
	mul.rn.f32 	%f247, %f246, %f58;
	add.f32 	%f459, %f247, 0f3F800000;
	bra.uni 	BB14_54;

BB14_53:
	mov.f32 	%f248, 0fB94CA1F9;
	mul.rn.f32 	%f249, %f248, %f58;
	add.f32 	%f250, %f249, 0f3C08839E;
	mul.rn.f32 	%f251, %f250, %f58;
	add.f32 	%f252, %f251, 0fBE2AAAA3;
	mul.rn.f32 	%f253, %f252, %f58;
	mul.rn.f32 	%f254, %f253, %f57;
	add.f32 	%f459, %f254, %f57;

BB14_54:
	and.b32  	%r146, %r55, 2;
	setp.eq.s32 	%p48, %r146, 0;
	neg.f32 	%f255, %f459;
	selp.f32 	%f460, %f459, %f255, %p48;
	bra.uni 	BB14_56;

BB14_55:
	mov.f32 	%f256, 0f00000000;
	mul.rn.f32 	%f460, %f193, %f256;

BB14_56:
	div.full.f32 	%f461, %f460, %f56;

BB14_57:
	mul.f32 	%f257, %f458, %f461;
	mad.f32 	%f476, %f257, %f413, %f476;
	mad.f32 	%f477, %f257, %f414, %f477;
	mad.f32 	%f478, %f257, %f415, %f478;
	mad.f32 	%f479, %f257, %f416, %f479;
	mad.f32 	%f462, %f458, %f461, %f462;
	add.s32 	%r186, %r186, 16;
	add.s32 	%r187, %r187, 1;
	setp.lt.u32 	%p49, %r187, %r112;
	@%p49 bra 	BB14_36;

	mov.f32 	%f463, 0f00000000;
	bra.uni 	BB14_60;

BB14_59:
	mov.f32 	%f463, 0f00000000;
	mov.f32 	%f476, %f463;
	mov.f32 	%f477, %f463;
	mov.f32 	%f478, %f463;
	mov.f32 	%f479, %f463;
	mov.f32 	%f462, %f463;

BB14_60:
	shl.b32 	%r147, %r103, 4;
	ld.param.u32 	%r177, [ResizeVerticalFilterSinc_param_19];
	add.s32 	%r58, %r177, %r147;
	shl.b32 	%r148, %r103, 2;
	ld.param.u32 	%r179, [ResizeVerticalFilterSinc_param_20];
	add.s32 	%r59, %r179, %r148;
	ld.param.u32 	%r181, [ResizeVerticalFilterSinc_param_21];
	add.s32 	%r60, %r181, %r148;
	setp.lt.u32 	%p5, %r103, %r32;
	setp.ge.u32 	%p50, %r103, %r32;
	@%p50 bra 	BB14_63;

	mov.f32 	%f264, 0f00000000;
	st.shared.v4.f32 	[%r58], {%f264, %f264, %f264, %f264};
	mov.u32 	%r149, 0;
	st.shared.u32 	[%r59], %r149;
	ld.param.u32 	%r164, [ResizeVerticalFilterSinc_param_3];
	setp.eq.s32 	%p51, %r164, 0;
	@%p51 bra 	BB14_63;

	st.shared.u32 	[%r60], %r149;

BB14_63:
	bar.sync 	0;
	setp.eq.s32 	%p52, %r35, 0;
	@%p52 bra 	BB14_70;

	shl.b32 	%r152, %r36, 4;
	ld.param.u32 	%r176, [ResizeVerticalFilterSinc_param_19];
	add.s32 	%r61, %r176, %r152;
	shl.b32 	%r153, %r36, 2;
	ld.param.u32 	%r178, [ResizeVerticalFilterSinc_param_20];
	add.s32 	%r62, %r178, %r153;
	ld.param.u32 	%r180, [ResizeVerticalFilterSinc_param_21];
	add.s32 	%r63, %r180, %r153;
	mov.u32 	%r188, 0;

BB14_65:
	@%p1 bra 	BB14_69;

	rem.u32 	%r154, %r103, %r35;
	setp.ne.s32 	%p53, %r188, %r154;
	@%p53 bra 	BB14_69;

	ld.shared.v4.f32 	{%f373, %f374, %f375, %f376}, [%r61];
	add.f32 	%f377, %f373, %f476;
	add.f32 	%f378, %f374, %f477;
	add.f32 	%f379, %f375, %f478;
	add.f32 	%f380, %f376, %f479;
	st.shared.v4.f32 	[%r61], {%f377, %f378, %f379, %f380};
	ld.shared.f32 	%f265, [%r62];
	add.f32 	%f266, %f265, %f462;
	st.shared.f32 	[%r62], %f266;
	ld.param.u32 	%r163, [ResizeVerticalFilterSinc_param_3];
	setp.eq.s32 	%p54, %r163, 0;
	@%p54 bra 	BB14_69;

	ld.shared.f32 	%f267, [%r63];
	add.f32 	%f268, %f267, %f463;
	st.shared.f32 	[%r63], %f268;

BB14_69:
	bar.sync 	0;
	add.s32 	%r188, %r188, 1;
	setp.lt.u32 	%p55, %r188, %r35;
	@%p55 bra 	BB14_65;

BB14_70:
	@!%p5 bra 	BB14_87;

	ld.shared.f32 	%f70, [%r59];
	setp.neu.f32 	%p56, %f70, 0f00000000;
	setp.neu.f32 	%p57, %f70, 0f3F800000;
	and.pred  	%p6, %p56, %p57;
	add.s32 	%r155, %r103, %r30;
	ld.param.u32 	%r167, [ResizeVerticalFilterSinc_param_6];
	mad.lo.s32 	%r156, %r155, %r167, %r19;
	shl.b32 	%r157, %r156, 4;
	ld.param.u32 	%r166, [ResizeVerticalFilterSinc_param_5];
	add.s32 	%r66, %r166, %r157;
	ld.param.u32 	%r162, [ResizeVerticalFilterSinc_param_3];
	setp.eq.s32 	%p58, %r162, 0;
	@%p58 bra 	BB14_81;

	ld.shared.f32 	%f465, [%r60];
	ld.shared.v4.f32 	{%f472, %f473, %f474, %f475}, [%r58];
	@%p6 bra 	BB14_73;
	bra.uni 	BB14_77;

BB14_73:
	setp.lt.f32 	%p59, %f70, 0f00000000;
	selp.f32 	%f72, 0fBF800000, 0f3F800000, %p59;
	mul.f32 	%f269, %f72, %f70;
	setp.ltu.f32 	%p60, %f269, 0f00000000;
	@%p60 bra 	BB14_75;

	rcp.approx.f32 	%f464, %f70;
	bra.uni 	BB14_76;

BB14_75:
	mul.f32 	%f464, %f72, 0f7F800000;

BB14_76:
	mul.f32 	%f472, %f472, %f464;
	mul.f32 	%f473, %f473, %f464;
	mul.f32 	%f474, %f474, %f464;
	mul.f32 	%f475, %f475, %f464;
	mul.f32 	%f465, %f465, %f464;

BB14_77:
	setp.lt.f32 	%p61, %f465, 0f00000000;
	selp.f32 	%f78, 0fBF800000, 0f3F800000, %p61;
	mul.f32 	%f273, %f78, %f465;
	setp.ltu.f32 	%p62, %f273, 0f00000000;
	@%p62 bra 	BB14_79;

	rcp.approx.f32 	%f466, %f465;
	bra.uni 	BB14_80;

BB14_79:
	mul.f32 	%f466, %f78, 0f7F800000;

BB14_80:
	mul.f32 	%f275, %f466, %f472;
	mov.f32 	%f276, 0f00000000;
	max.f32 	%f277, %f275, %f276;
	mov.f32 	%f278, 0f477FFF00;
	min.f32 	%f279, %f277, %f278;
	add.f32 	%f280, %f279, 0f3F000000;
	mul.f32 	%f282, %f466, %f473;
	max.f32 	%f283, %f282, %f276;
	min.f32 	%f284, %f283, %f278;
	add.f32 	%f285, %f284, 0f3F000000;
	mul.f32 	%f287, %f466, %f474;
	max.f32 	%f288, %f287, %f276;
	min.f32 	%f289, %f288, %f278;
	add.f32 	%f290, %f289, 0f3F000000;
	max.f32 	%f292, %f475, %f276;
	min.f32 	%f293, %f292, %f278;
	add.f32 	%f294, %f293, 0f3F000000;
	st.global.v4.f32 	[%r66], {%f280, %f285, %f290, %f294};
	bra.uni 	BB14_87;

BB14_81:
	ld.shared.v4.f32 	{%f468, %f469, %f470, %f471}, [%r58];
	@%p6 bra 	BB14_82;
	bra.uni 	BB14_86;

BB14_82:
	setp.lt.f32 	%p63, %f70, 0f00000000;
	selp.f32 	%f82, 0fBF800000, 0f3F800000, %p63;
	mul.f32 	%f295, %f82, %f70;
	setp.ltu.f32 	%p64, %f295, 0f00000000;
	@%p64 bra 	BB14_84;

	rcp.approx.f32 	%f467, %f70;
	bra.uni 	BB14_85;

BB14_84:
	mul.f32 	%f467, %f82, 0f7F800000;

BB14_85:
	mul.f32 	%f468, %f468, %f467;
	mul.f32 	%f469, %f469, %f467;
	mul.f32 	%f470, %f470, %f467;
	mul.f32 	%f471, %f471, %f467;

BB14_86:
	mov.f32 	%f300, 0f00000000;
	max.f32 	%f301, %f468, %f300;
	mov.f32 	%f302, 0f477FFF00;
	min.f32 	%f303, %f301, %f302;
	add.f32 	%f304, %f303, 0f3F000000;
	max.f32 	%f306, %f469, %f300;
	min.f32 	%f307, %f306, %f302;
	add.f32 	%f308, %f307, 0f3F000000;
	max.f32 	%f310, %f470, %f300;
	min.f32 	%f311, %f310, %f302;
	add.f32 	%f312, %f311, 0f3F000000;
	max.f32 	%f314, %f471, %f300;
	min.f32 	%f315, %f314, %f302;
	add.f32 	%f316, %f315, 0f3F000000;
	st.global.v4.f32 	[%r66], {%f304, %f308, %f312, %f316};

BB14_87:
	add.s32 	%r184, %r184, 1;
	setp.lt.u32 	%p65, %r184, %r25;
	ld.param.u32 	%r174, [ResizeVerticalFilterSinc_param_18];
	sub.s32 	%r183, %r183, %r174;
	@%p65 bra 	BB14_7;

BB14_88:
	ret;
}