From c09d215f1cc6fc90c4b6265cf3ca77f5c1120674 Mon Sep 17 00:00:00 2001 From: android Date: Fri, 29 Oct 2021 16:27:24 -0700 Subject: [PATCH] The included patch corrects an MTE detection bug in gdbserver 11.1 There is an upstream bug report: https://sourceware.org/bugzilla/show_bug.cgi?id=28355 From the upstream report: "If one has a kernel new enough that it has MTE awareness, and use a new enough gdbserver that knows about the tag_ctl register, it will run into this situation." The text of the error from gdbserver: ../../gdbserver/regcache.cc:257: A problem internal to GDBserver has been detected. Unknown register tag_ctl requested This bug only affects gdbserver 11.1. Signed-off-by: android --- trunk/PKGBUILD | 13 +- trunk/gdbserver-mte.patch | 292 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 301 insertions(+), 4 deletions(-) create mode 100644 trunk/gdbserver-mte.patch diff --git a/trunk/PKGBUILD b/trunk/PKGBUILD index 935f33a..f8d513d 100644 --- a/trunk/PKGBUILD +++ b/trunk/PKGBUILD @@ -8,19 +8,22 @@ pkgbase=gdb # of gdb (for arm/avr/...) pkgname=(gdb gdb-common) pkgver=11.1 -pkgrel=1 +pkgrel=2 pkgdesc='The GNU Debugger' arch=(x86_64) url='https://www.gnu.org/software/gdb/' license=(GPL3) makedepends=(glibc gcc-libs texinfo python guile ncurses expat xz mpfr source-highlight readline) -source=(https://ftp.gnu.org/gnu/gdb/${pkgname}-${pkgver}.tar.xz{,.sig}) +source=(https://ftp.gnu.org/gnu/gdb/${pkgname}-${pkgver}.tar.xz{,.sig} + gdbserver-mte.patch) sha1sums=('6cb3361c7f2b22d6d2c25ab4992264aa41bc2471' - 'SKIP') + 'SKIP' + 'da5272584ab98947d13c8a393f7a62f91de57654') b2sums=('6a639f6533f4008bfb469c23a26c4fcd039f1bc5dd33745f4876344451beb595d7a8843caeb5db70214924624c5b999f8831237d459bebf1cb2d2866f8b41ee2' - 'SKIP') + 'SKIP' + 'b2d9a569c51b241b780edcdad8ff601eb99106af810890be928f4a099fed6817d8b41574f82d01b8c88f1032ce671275046a63810c369552cb5c9cf6c7f89eea') validpgpkeys=('F40ADB902B24264AA42E50BF92EDB04BFF325CF3') # Joel Brobecker prepare() { @@ -33,6 +36,8 @@ prepare() { build() { cd gdb-$pkgver + patch -Np1 -i ${srcdir}/gdbserver-mte.patch + mkdir -p build && cd build ../configure \ --prefix=/usr \ diff --git a/trunk/gdbserver-mte.patch b/trunk/gdbserver-mte.patch new file mode 100644 index 0000000..e2030fb --- /dev/null +++ b/trunk/gdbserver-mte.patch @@ -0,0 +1,292 @@ +From 42a5e5b93467b1aba670cec4adae4605671f7c63 Mon Sep 17 00:00:00 2001 +From: Luis Machado +Date: Fri, 29 Oct 2021 14:54:36 -0300 +Subject: [PATCH] [AArch64] Make gdbserver register set selection dynamic + +The current register set selection mechanism for AArch64 is static, based +on a pre-populated array of register sets. + +This means that we might potentially probe register sets that are not +available. This is OK if the kernel errors out during ptrace, but probing the +tag_ctl register, for example, does not result in a ptrace error if the kernel +supports the tagged address ABI but not MTE. + +Making the register set selection dynamic, based on feature checks, solves +this and simplifies the code a bit. It allows us to list all of the register +sets only once, and pick and choose based on HWCAP/HWCAP2 or other properties. +--- + gdb/arch/aarch64.h | 9 ++ + gdbserver/linux-aarch64-low.cc | 185 ++++++++++++++++++--------------- + 2 files changed, 110 insertions(+), 84 deletions(-) + +diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h +index 0eb702c5b5e..95edb664b55 100644 +--- a/gdb/arch/aarch64.h ++++ b/gdb/arch/aarch64.h +@@ -22,6 +22,15 @@ + + #include "gdbsupport/tdesc.h" + ++/* Holds information on what architectural features are available. This is ++ used to select register sets. */ ++struct aarch64_features ++{ ++ bool sve = false; ++ bool pauth = false; ++ bool mte = false; ++}; ++ + /* Create the aarch64 target description. A non zero VQ value indicates both + the presence of SVE and the Vector Quotient - the number of 128bit chunks in + an SVE Z register. HAS_PAUTH_P indicates the presence of the PAUTH +diff --git a/gdbserver/linux-aarch64-low.cc b/gdbserver/linux-aarch64-low.cc +index daccfef746e..d056aeeae44 100644 +--- a/gdbserver/linux-aarch64-low.cc ++++ b/gdbserver/linux-aarch64-low.cc +@@ -196,16 +196,6 @@ is_64bit_tdesc (void) + return register_size (regcache->tdesc, 0) == 8; + } + +-/* Return true if the regcache contains the number of SVE registers. */ +- +-static bool +-is_sve_tdesc (void) +-{ +- struct regcache *regcache = get_thread_regcache (current_thread, 0); +- +- return tdesc_contains_feature (regcache->tdesc, "org.gnu.gdb.aarch64.sve"); +-} +- + static void + aarch64_fill_gregset (struct regcache *regcache, void *buf) + { +@@ -680,40 +670,6 @@ aarch64_target::low_new_fork (process_info *parent, + *child->priv->arch_private = *parent->priv->arch_private; + } + +-/* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */ +-#define AARCH64_HWCAP_PACA (1 << 30) +- +-/* Implementation of linux target ops method "low_arch_setup". */ +- +-void +-aarch64_target::low_arch_setup () +-{ +- unsigned int machine; +- int is_elf64; +- int tid; +- +- tid = lwpid_of (current_thread); +- +- is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine); +- +- if (is_elf64) +- { +- uint64_t vq = aarch64_sve_get_vq (tid); +- unsigned long hwcap = linux_get_hwcap (8); +- unsigned long hwcap2 = linux_get_hwcap2 (8); +- bool pauth_p = hwcap & AARCH64_HWCAP_PACA; +- /* MTE is AArch64-only. */ +- bool mte_p = hwcap2 & HWCAP2_MTE; +- +- current_process ()->tdesc +- = aarch64_linux_read_description (vq, pauth_p, mte_p); +- } +- else +- current_process ()->tdesc = aarch32_linux_read_description (); +- +- aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread)); +-} +- + /* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */ + + static void +@@ -730,20 +686,36 @@ aarch64_sve_regs_copy_from_regcache (struct regcache *regcache, void *buf) + return aarch64_sve_regs_copy_from_reg_buf (regcache, buf); + } + ++/* Array containing all the possible register sets for AArch64/Linux. During ++ architecture setup, these will be checked against the HWCAP/HWCAP2 bits for ++ validity and enabled/disabled accordingly. ++ ++ Their sizes are set to 0 here, but they will be adjusted later depending ++ on whether each register set is available or not. */ ++ + static struct regset_info aarch64_regsets[] = + { ++ /* GPR registers. */ + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, +- sizeof (struct user_pt_regs), GENERAL_REGS, ++ 0, GENERAL_REGS, + aarch64_fill_gregset, aarch64_store_gregset }, ++ /* Floating Point (FPU) registers. */ + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, +- sizeof (struct user_fpsimd_state), FP_REGS, ++ 0, FP_REGS, + aarch64_fill_fpregset, aarch64_store_fpregset + }, ++ /* Scalable Vector Extension (SVE) registers. */ ++ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE, ++ 0, EXTENDED_REGS, ++ aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache ++ }, ++ /* PAC registers. */ + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK, +- AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS, +- NULL, aarch64_store_pauthregset }, ++ 0, OPTIONAL_REGS, ++ nullptr, aarch64_store_pauthregset }, ++ /* Tagged address control / MTE registers. */ + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL, +- AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset, ++ 0, OPTIONAL_REGS, aarch64_fill_mteregset, + aarch64_store_mteregset }, + NULL_REGSET + }; +@@ -752,47 +724,95 @@ static struct regsets_info aarch64_regsets_info = + { + aarch64_regsets, /* regsets */ + 0, /* num_regsets */ +- NULL, /* disabled_regsets */ ++ nullptr, /* disabled_regsets */ + }; + + static struct regs_info regs_info_aarch64 = + { +- NULL, /* regset_bitmap */ +- NULL, /* usrregs */ ++ nullptr, /* regset_bitmap */ ++ nullptr, /* usrregs */ + &aarch64_regsets_info, + }; + +-static struct regset_info aarch64_sve_regsets[] = ++/* Given FEATURES, adjust the available register sets by setting their ++ sizes. A size of 0 means the register set is disabled and won't be ++ used. */ ++ ++static void ++aarch64_adjust_register_sets (const struct aarch64_features &features) + { +- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, +- sizeof (struct user_pt_regs), GENERAL_REGS, +- aarch64_fill_gregset, aarch64_store_gregset }, +- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE, +- SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE), EXTENDED_REGS, +- aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache +- }, +- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK, +- AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS, +- NULL, aarch64_store_pauthregset }, +- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL, +- AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset, +- aarch64_store_mteregset }, +- NULL_REGSET +-}; ++ struct regset_info *regset; + +-static struct regsets_info aarch64_sve_regsets_info = +- { +- aarch64_sve_regsets, /* regsets. */ +- 0, /* num_regsets. */ +- NULL, /* disabled_regsets. */ +- }; ++ for (regset = aarch64_regsets; regset->size >= 0; regset++) ++ { ++ switch (regset->nt_type) ++ { ++ case NT_PRSTATUS: ++ /* General purpose registers are always present. */ ++ regset->size = sizeof (struct user_pt_regs); ++ break; ++ case NT_FPREGSET: ++ /* This is unavailable when SVE is present. */ ++ if (!features.sve) ++ regset->size = sizeof (struct user_fpsimd_state); ++ break; ++ case NT_ARM_SVE: ++ if (features.sve) ++ regset->size = SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE); ++ break; ++ case NT_ARM_PAC_MASK: ++ if (features.pauth) ++ regset->size = AARCH64_PAUTH_REGS_SIZE; ++ break; ++ case NT_ARM_TAGGED_ADDR_CTRL: ++ if (features.mte) ++ regset->size = AARCH64_LINUX_SIZEOF_MTE; ++ break; ++ default: ++ gdb_assert_not_reached ("Unknown register set found."); ++ } ++ } ++} + +-static struct regs_info regs_info_aarch64_sve = +- { +- NULL, /* regset_bitmap. */ +- NULL, /* usrregs. */ +- &aarch64_sve_regsets_info, +- }; ++/* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */ ++#define AARCH64_HWCAP_PACA (1 << 30) ++ ++/* Implementation of linux target ops method "low_arch_setup". */ ++ ++void ++aarch64_target::low_arch_setup () ++{ ++ unsigned int machine; ++ int is_elf64; ++ int tid; ++ ++ tid = lwpid_of (current_thread); ++ ++ is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine); ++ ++ if (is_elf64) ++ { ++ struct aarch64_features features; ++ ++ uint64_t vq = aarch64_sve_get_vq (tid); ++ features.sve = (vq > 0); ++ /* A-profile PAC is 64-bit only. */ ++ features.pauth = linux_get_hwcap (8) & AARCH64_HWCAP_PACA; ++ /* A-profile MTE is AArch64-only. */ ++ features.mte = linux_get_hwcap2 (8) & HWCAP2_MTE; ++ ++ current_process ()->tdesc ++ = aarch64_linux_read_description (vq, features.pauth, features.mte); ++ ++ /* Adjust the register sets we should use for this particular set of ++ features. */ ++ aarch64_adjust_register_sets (features); ++ } ++ else ++ current_process ()->tdesc = aarch32_linux_read_description (); ++ ++ aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread)); ++} + + /* Implementation of linux target ops method "get_regs_info". */ + +@@ -802,9 +822,7 @@ aarch64_target::get_regs_info () + if (!is_64bit_tdesc ()) + return ®s_info_aarch32; + +- if (is_sve_tdesc ()) +- return ®s_info_aarch64_sve; +- ++ /* AArch64 64-bit registers. */ + return ®s_info_aarch64; + } + +@@ -3294,5 +3312,4 @@ initialize_low_arch (void) + initialize_low_arch_aarch32 (); + + initialize_regsets_info (&aarch64_regsets_info); +- initialize_regsets_info (&aarch64_sve_regsets_info); + } +-- +2.25.1 + -- 2.33.1