From 3fb9798153dafed3935e49e3d7aebd6c419b387d Mon Sep 17 00:00:00 2001 From: Jeff Cook Date: Mon, 19 Jun 2017 03:52:44 -0400 Subject: [PATCH] Fix bad codegen in gcc. --- gcc/repos/core-x86_64/PKGBUILD | 11 +++-- ...nvalid-patterns-for-builtin-clz-bug-81015.patch | 54 ++++++++++++++++++++++ 2 files changed, 62 insertions(+), 3 deletions(-) create mode 100644 gcc/repos/core-x86_64/Remove-invalid-patterns-for-builtin-clz-bug-81015.patch diff --git a/gcc/repos/core-x86_64/PKGBUILD b/gcc/repos/core-x86_64/PKGBUILD index 3d8845d..bb904fd 100644 --- a/gcc/repos/core-x86_64/PKGBUILD +++ b/gcc/repos/core-x86_64/PKGBUILD @@ -8,7 +8,7 @@ pkgname=('gcc' 'gcc-libs' 'gcc-fortran' 'gcc-objc' 'gcc-ada' 'gcc-go') pkgver=7.1.1 _pkgver=${pkgver:0:1} _islver=0.18 -pkgrel=2 +pkgrel=3 _commit=754d7e56674dda4bd2d40e310d2093c2df970780 pkgdesc="The GNU Compiler Collection" arch=('i686' 'x86_64') @@ -19,10 +19,12 @@ checkdepends=('dejagnu' 'inetutils') options=('!emptydirs') source=(git+https://gcc.gnu.org/git/gcc.git#commit=${_commit} http://isl.gforge.inria.fr/isl-${_islver}.tar.bz2 - Revert-eeb6872bf.patch) + Revert-eeb6872bf.patch + Remove-invalid-patterns-for-builtin-clz-bug-81015.patch) md5sums=('SKIP' '11436d6b205e516635b666090b94ab32' - 'e4c9c8b498b04c0f51d219d025ca8407') + 'e4c9c8b498b04c0f51d219d025ca8407' + 'a32dc8e8a037cada3b843b7dbc6ce02c') _libdir="usr/lib/gcc/$CHOST/$pkgver" @@ -44,6 +46,9 @@ prepare() { # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80717 git apply ../Revert-eeb6872bf.patch + # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81015 + git apply ../Remove-invalid-patterns-for-builtin-clz-bug-81015.patch + mkdir ${srcdir}/gcc-build } diff --git a/gcc/repos/core-x86_64/Remove-invalid-patterns-for-builtin-clz-bug-81015.patch b/gcc/repos/core-x86_64/Remove-invalid-patterns-for-builtin-clz-bug-81015.patch new file mode 100644 index 0000000..149bbc2 --- /dev/null +++ b/gcc/repos/core-x86_64/Remove-invalid-patterns-for-builtin-clz-bug-81015.patch @@ -0,0 +1,54 @@ +diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md +index a2a163a..adc13a9 100644 +--- a/gcc/config/i386/i386.md ++++ b/gcc/config/i386/i386.md +@@ -12762,24 +12762,6 @@ + (set_attr "znver1_decode" "vector") + (set_attr "mode" "")]) + +-(define_insn_and_split "*ctzhi2" +- [(set (match_operand:SI 0 "register_operand") +- (ctz:SI +- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand")))) +- (clobber (reg:CC FLAGS_REG))] +- "TARGET_BMI +- && can_create_pseudo_p ()" +- "#" +- "&& 1" +- [(const_int 0)] +-{ +- rtx tmp = gen_reg_rtx (HImode); +- +- emit_insn (gen_tzcnt_hi (tmp, operands[1])); +- emit_insn (gen_zero_extendhisi2 (operands[0], tmp)); +- DONE; +-}) +- + (define_insn_and_split "ctz2" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (ctz:SWI48 +@@ -12899,24 +12881,6 @@ + operands[2] = GEN_INT (GET_MODE_BITSIZE (mode)-1); + }) + +-(define_insn_and_split "*clzhi2" +- [(set (match_operand:SI 0 "register_operand") +- (clz:SI +- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand")))) +- (clobber (reg:CC FLAGS_REG))] +- "TARGET_LZCNT +- && can_create_pseudo_p ()" +- "#" +- "&& 1" +- [(const_int 0)] +-{ +- rtx tmp = gen_reg_rtx (HImode); +- +- emit_insn (gen_lzcnt_hi (tmp, operands[1])); +- emit_insn (gen_zero_extendhisi2 (operands[0], tmp)); +- DONE; +-}) +- + (define_insn_and_split "clz2_lzcnt" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (clz:SWI48 -- 2.13.1